Applied Materials, Inc.

Sunderraj Thirupapuliyur

Faran Nouri

Christopher Sean Olsen

Wei Liu

Johanes F Swenberg

Shiyu Sun

Jacob Newman

Jing Tang

Tze Wing Poon

Udayan Ganguly

Yonah Cho

Vicky U Nguyen

Lori D Washington

Vijay Parihar

Sean M Seutter

Swaminathan T Srinivasan

Andrew C Lam

Yoshitaka Yokota

Yuji Maeda

Jacob W Smith

R Suryanarayanan Iyer

Sanjeev Tandon

Thomas Mele

Randhir P Singh Thakur

Yoshita Yokota

Eun-Ha Kim

Swaminathar Srinivasan

Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof

NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, an NMOS transistor may include a transistor stack comprising a gate dielectric and a gate electrode formed atop a p-type silicon region; and a source/drain region disposed on both sides of the transistor stack and defining a channel region therebetween and beneath the transistor stack, the source drain region including a first silicon layer having a lattice adjusting element and one or more second silicon layers having a lattice adjusting element and an n-type dopant disposed atop the first silicon layer.

NMOS transistor devices and methods for fabricating same

Methods are provided for manufacturing transistors and altering the stress in the channel region of a single transistor. One or more parameters that are effect stress in the channel region are altered for a single transistor to increase or decrease the channel stress in PMOS and NMOS transistors.

Methods for forming a transistor and modulating channel stress

NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include providing a substrate having a p-type silicon region and a gate stack disposed thereon, the gate stack partially defining a source and a drain region; depositing an undoped first silicon layer having a lattice adjusting element atop the p-type silicon region and within the source and the drain regions; and depositing a second silicon layer having a lattice adjusting element and an n-type dopant atop the undoped first silicon layer.

Methods for reducing contact resistance in semiconductor devices are provided in the present invention. In one embodiment, the method includes providing a substrate having semiconductor device formed thereon, wherein the device has source and drain regions and a gate structure formed therein, performing a silicidation process on the substrate by a thermal annealing process, and performing a laser anneal process on the substrate. In another embodiment, the method includes providing a substrate having implanted dopants, performing a silicidation process on the substrate by a thermal annealing process, and activating the dopants by a laser anneal process.

Methods for contact resistance reduction of advanced CMOS devices

Defects and fixed charge in a gate dielectric near the gate dielectric-substrate interface are reduced by performing a gate dielectric relaxation anneal step prior to source-drain ion implantation, in which the wafer temperature is ramped gradually to near a melting temperature of the substrate equal to a peak post-ion implantation anneal peak temperature. The ramping rates are sufficiently gradual so that the gate dielectric is held above its reflow temperature for a significant duration.

Gate interface relaxation anneal method for wafer processing with post-implant dynamic surface annealing

An assembly comprises a multilayer nitride stack having nitride etch stop layers formed on top of one another, each of the nitride etch stop layers is formed using a film forming process. A method of making the multilayer nitride stack includes placing a substrate in a single wafer deposition chamber and thermally shocking the substrate momentarily prior to deposition. A first nitride etch stop layer is deposited over the substrate. A second nitride etch stop layer is deposited over the first nitride etch stop layer.

Silicon nitride film with stress control

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San Jose, CA, United States of America

Sunderraj Thirupapuliyur