Barcelona Design, Inc.

Sunderarajan S Mohan

Dan Bui

Paul B Morton

An oscillator delay stage is described. The oscillator delay stage includes at least one differential input; a pair of single ended inverters for each differential input; and, a differential output. With respect to the pair of single ended inverters for each differential input, each pair of single ended inverters further include for their corresponding differential input: i) a first single ended inverter whose input is coupled to a + input of the corresponding differential input; and, ii) a second single ended inverter whose input is coupled to a &#x2212; input of the corresponding differential input. With respect to the differential output, the differential input further includes: i) a + output that is coupled to each said second single ended inverter output; ii) a &#x2212; output that is coupled to each said first single ended inverter output.

Delay stage for oscillator circuit and corresponding applications

Methods are described that involve characterizing an oscillator's jitter or phase noise over a plurality of the oscillator's effective number of delay stages. The oscillator comprises a series of delay stages. Each one of the effective number of delay stages, if selected for the oscillator, describes a respective permissible range of inverter drive strengths that may be used within each delay stage of the oscillator to achieve a respective jitter or phase noise characteristic.

Methodology for design of oscillator delay stage and corresponding applications

A power distribution circuit built with wiring layers that reside above an analog circuit is described. The power distribution circuit comprises one or more capacitive structures that reside above the analog circuit. At least one of the one or more capacitive structures has electrodes that provide supply and/or reference voltages and their corresponding currents to said analog circuit. A machine readable medium is described to perform a method in order to design the power distribution circuit. The method includes: assigning a specific supply or reference voltage to each of the electrodes; and, determining wiring dimensions for each of the electrodes. The wiring dimensions for the electrodes of at least one of the capacitive structures is are based at least in part on IR drop concerns.

Growing community of inventors

Menlo Park, CA, United States of America

Sunderarajan S Mohan