Netlogic Microsystems, Inc

Lucent Technologies Inc.

Alcatel-lucent USA Inc.

Sunder Raj Rathnavelu

Jose Pio Pereira

Ronald S Jankov

David Way Ng

Rodolfo G Beraha

Lewis M Carroll

Sandeep Khanna

Dimitrios Stiliadis

Vijay Pochampalli Kumar

Hong-Yi Tzeng

Chinh Kim Nguyen

W Steven Lo

Raman Arunachalam

Don Tipon

A scalable, high-speed router for routing packets of information through an interconnected network comprises an interface for receiving a packet containing header and data information; a device for extracting routing information from the header of an arrived packet and generating a corresponding header packet for the arrived packet; a memory device for storing the data information of the arrived packet at predetermined memory locations; a device for processing the corresponding header packet to determine a route for the arrived packet and assigning packet forwarding information to the header packet; and, a device for retrieving the data information from the predetermined memory locations and forwarding both the data and header packet containing the packet forwarding information to the interface for routing the packet to a further destination in accordance with the packet forwarding information. The processing device includes devices performing filtering, route-table lookup and flow identification functions and which devices are organized in a pipelined fashion for successive, high-speed operations on the header packet. The router ensures that the arrived packet is forwarded in accordance with any quality of service requirements and flow specifications.

Scalable high speed router apparatus

A content addressable memory device including a memory to store a searchable database, a search circuit, and a first-in-first-out storage circuit. The search circuit generates a plurality of address values that correspond to unoccupied storage locations within the memory, and the plurality of address values are queued within the first-in-first-out storage circuit to enable the address values to be read in succession by an external device.

Block-writable content addressable memory device

An apparatus and method for generating a comparand in a content addressable memory array. For one embodiment, the apparatus includes a content addressable memory (CAM) array and translation circuitry. The CAM array receives a comparand and the translation circuitry includes at least one first input, at least one second input, and at least one output. The first input is configured to receive an input data having a plurality of bit groups, wherein a first bit group has a first position in the input data relative to other bit groups. The second input is configured to receive translation information indicative of translation of the first bit group from the first position to a different position in a comparand. The output is coupled to the CAM array to transmit the comparand to the CAM array. For one example, the translation circuitry includes a switch circuit that may include one or more multiplexers or demultiplexers. The translation circuitry may also include one or more storage elements to store the translation information, and one or more decode circuitry to decode the translation information and establish switch circuit connections between the first position and the position in the comparand.

Comparand generation in a content addressable memory

A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the index from the index generator and outputs a stored data value from a location indicated by the index. A compare circuit receives the data value from the memory and compares the data value and the search value to generate a match signal indicative of whether the data value and search value match. The match signal and index are output from the CAM device.

Content addressable memory device

Content addressable memory with hashing function

Streams of information are transmitted over corresponding channels of an information network, by associating a number of queues with the channels, enqueuing incoming descriptors representing information to be transmitted over a given channel in a queue associated with the channel, and dequeuing the descriptors from the queues by operation of a scheduler. A small and fixed-size buffer is associated with each channel, and a watermark threshold value corresponding to a minimum occupancy level is defined for each of the transmit buffers. When the occupancy of a given buffer falls below the buffer's threshold value, a corresponding watermark event signal identifying the channel associated with the buffer is produced. The watermark event signals are provided to the scheduler, and information represented by descriptors dequeued by the scheduler are delivered to corresponding buffers according to the order of the watermark event signals provided to the scheduler.

Packet transmission scheduling with threshold based backpressure mechanism

Entry relocation in a content addressable memory (CAM) device. The CAM device is instructed to store a first value and to supply an address at which the first value is stored. If the address indicates that the first value has been stored within an overflow storage array of the CAM device, the CAM device is instructed to store the first value again.

Entry relocation in a content addressable memory device

A scheduling mechanism for satisfying specified Quality of Service guarantees for each VC of an end-point host in an ATM network and for satisfying low latency requirements of certain VCs while maintaining high throughput. The scheduling mechanism includes at least one time slot ring, a VC table and at least two pending queues. The time slot ring is an array of time slots grouped into clusters. Each slot contains a pointer which contains the virtual channel identifier to be serviced. The VC table is an array of all the VC descriptors. The pending queues are used for queuing a new VC and when the scheduler is unable to find a time slot for a VC it is queued in the pending queue. One pending queue is restricted to VCs requiring low latency and thus need to be serviced prior to servicing other VCs not sharing the same low latency requirements. A second pending queue is used for VCs with a less critical latency requirement. The ring contains cluster pointers which point to the first VC to be serviced. The rest of the VCs in the cluster are linked to the first VC. In order to accommodate different classes of service, each entry in the ring holds multiple cluster pointers. The scheduler first processes all low latency VCs, and then circularly reads and processes one cluster at a time at the maximum speed allowed by the physical link, and a current slot pointer points to the slot being serviced. For the current time slot, the scheduler first services the VC waiting on this slot, then schedules a new target time slot for this VC after marking the current slot empty.

Adaptive time slot scheduling apparatus and method for end-points in an ATM network

Adaptive time slot scheduling apparatus and method for end-points in an

A scheduling mechanism for satisfying specified Quality of Service (QoS) guarantees for each VC of an end-point host in an ATM network. The scheduling mechanism includes a time slot ring, a VC table and a pending queue. The time slot ring is an array, wherein each element represents a time slot. Each slot contains a pointer which contains the virtual channel identifier (VCID) which is to be serviced in this time slot. The VC table is an array of all the VC descriptors. The pending queue is used for queuing a new VC and also at a later time, when the scheduler is unable to find a time slot for a VC it is queued in the pending queue. The scheduler reads and processes one slot at a time at the maximum speed that the physical link will allow. The scheduler circularly services the slots in the ring continuously and a current slot pointer (CSP) points to the slot being serviced. For the current time slot, the scheduler first services the VC waiting on this slot, then schedules a new target time slot for this VC after marking the current slot empty. The target slot is calculated based on a cell-to-cell spacing parameter and a remainder mechanism is used to correct the average output cell rate to a required rate. In an alternate embodiment, the time slots within the ring are grouped into clusters. The ring contains cluster pointers which point to the first VC to be serviced. The rest of the VCs in the cluster are linked to the first VC. In order to accommodate different classes of service, each entry in the ring holds multiple cluster pointers.

An apparatus an method for adaptive time slot scheduling of communications traffic generated by end-point host in ATM network. The scheduler includes a time slot ring including an array of time slots, wherein each of said time slots includes a virtual channel identifier (VCID) of a virtual channel (VC) to be serviced; a VC table including an array of VC descriptors, wherein the VCID stored in said time slot ring points to a VC descriptor in the VC table; and processor for scheduling the VCs in said time slots of said time slot ring, wherein the time slots ring are circularly processed in a continuous fashion thereby enabling scheduled transmission of ATM cells in the network. The processor is operable to queue the VCID of a newly calculated target slot in an already occupied time slot if the newly calculated target slot is occupied, thereby creating a linked list of VCs, and the processor is operable to service all VCs at a single time slot before proceeding to a next time slot.

Growing community of inventors

Marlboro, NJ, United States of America

Sunder Raj Rathnavelu