Amkor Technology, Inc.

Skyworks Solutions, Inc.

Jds Uniphase Corporation

Sundeep Nand Nangalia

Robert Lanzone

Karthikeyan Dhandapani

Richard Raymond Green

Ahmer Raza Syed

Dean Zehnder

Robert Francis Darveaux

Russ Alan Reisner

David Peter Gaio

William K Hogan

Ki Wook Lee

John C Baldwin

Miles Frank Swain

Takeshi Furusawa

Christopher M Gabel

Philip Deane

Roger T Lindquist

Ravi Kiran Chilukuri

Marian C Hargis

James Walling

Riki Whiting

Rich Green

Kyle Gilliland

Rex Beach Anderson, Iii

Devices and methods related to nested filters. In some embodiments, a radio-frequency device can include a substrate, and first and second filter devices mounted on the substrate with respective support structures, such that at least a portion of the second filter device is positioned in a space defined by an underside of the first filter device and the support structures for the first filter device. Such a radio-frequency device can be, for example, a packaged module for use in an electronic device such as a wireless device.

Devices and methods related to nested filters

Methods and systems for a robust pillar structure for a semiconductor device contacts are disclosed, and may include processing a semiconductor wafer comprising one or more metal pads, wherein the processing may comprise: forming a second metal contact on the one or more metal pads; forming a pillar on the second metal contact, and forming a solder bump on the second metal contact and the pillar, wherein the pillar extends into the solder bump. The second metal contact may comprise a stepped mushroom shaped bump, a sloped mushroom shaped bump, a cylindrical post, and/or a redistribution layer. The semiconductor wafer may comprise silicon. A solder brace layer may be formed around the second metal contact. The second metal contact may be tapered down to a smaller area at the one or more metal pads on the semiconductor wafer. A seed layer may be formed between the second metal contact and the one or more metal pads on the semiconductor wafer. The pillar may comprise copper.

Robust pillar structure for semicondcutor device contacts

An electronic component structure includes a primary redistribution structure having a primary redistribution structure terminal. A secondary redistribution structure is formed on the primary redistribution structure terminal. A buildup dielectric layer encloses the primary redistribution structure, where a cushion pad of the secondary redistribution structure is supported by the buildup dielectric layer. An interconnection ball is mounted to the secondary redistribution structure. Stress imparted upon the interconnection ball is transferred through the secondary redistribution structure and dissipated to the buildup dielectric layer through the cushion pad. The buildup dielectric layer is readily able to absorb this stress thus minimizing the probability of failure of the secondary redistribution structure including the interconnection ball formed thereon.

Electronic component package fabrication method and structure

Systems, methods and/or techniques for mushroom shaped bump on repassivation are described. A method of forming a chip scale package may include applying a first photoresist layer over a semiconductor wafer, developing away a portion of the first photoresist layer to define a cylindrically shaped template with substantially vertical side walls, and plating metal at least partially within the template to form a bump. The bump may include a first cylindrical base portion, a cap, and a lip formed by a portion of the cap that extends horizontally outward beyond the first cylindrical base portion. The cap and lip may be formed such that a vertical distance exists between the lip and the semiconductor wafer, defining an intrusion area. The method may include removing excess portions of the first photoresist layer, including portions residing in the intrusion area, to isolate the bump.

Mushroom shaped bump on repassivation

Systems, methods and/or techniques for processing solderbrace using one or more light wavelength filters are described. A method of processing solderbrace material may include applying solderbrace material to a wafer, placing a light wavelength filter between the solderbrace material and a broadband light source and exposing the light wavelength filter to broadband light from the broadband light source. The light wavelength filter may block some wavelengths of light and may allow other wavelengths of light to pass through and strike the solderbrace material. In some embodiments, the light wavelength filter may be an I-Line filter that is adapted to block substantially all wavelengths of light and allow passage of I-Line wavelengths of light. In some embodiments, the light wavelength filter may be an I-Line filter that is adapted to block substantially all G-Line and H-Line wavelengths of light and allow passage of substantially all I-Line wavelengths of light.

Processing solderbrace using light wavelength filter and a broadband light source

A method includes forming a first buildup dielectric layer on a wafer. The wafer includes electronic components delineated from one another by singulation streets. A singulation street exposure light trap layer is formed on the singulation streets. A second buildup dielectric layer is applied and patterned by being selectively exposed to an exposure light. The singulation street exposure light trap layer traps and diffuses the exposure light thus preventing the exposure light from being reflected to the portion of the second buildup dielectric layer above the singulation streets. In this manner, complete removal of the second buildup dielectric layer above the singulation streets is insured.

Electronic component package fabrication method

An electronic component package includes a RDL pattern comprising a redistribution pattern terminal. A buildup dielectric layer is formed on the RDL pattern, the buildup dielectric layer having a redistribution pattern terminal aperture exposing the redistribution pattern terminal. An interconnection ball is formed within the redistribution pattern terminal aperture and on the redistribution pattern terminal. The interconnection ball includes an enclosed portion having an outer concave surface within the buildup dielectric layer. The angle of intersection between the outer concave surface of the interconnection ball and the redistribution pattern is less than 90&#xb0;. This minimizes stress between the interconnection ball and the redistribution pattern which, in turn, minimizes failure of the bond between the interconnection ball and the redistribution pattern.

The invention relates to an optical sub-assembly package for use in receiver optical sub-assemblies or transmitter optical sub-assemblies in which the electrical connections between the transducer chip, e.g. photo-detector or light source, and the device printed circuit board is made by a single flexible circuit conductor extending through the wall of the package. The package is comprised of a housing and a stiffening plate, which encloses and end of the housing and forms a mechanical support for an end of the flexible circuit conductor.

Compact optical sub-assembly with integrated flexible circuit

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Raleigh, NC, United States of America

Sundeep Nand Nangalia