International Business Machines Corporation

Sundeep Chadha

Dung Q Nguyen

David R Terry

Brian William Thompto

Hung Qui Le

Brian David Barrick

David Allen Hrusecky

Michael Joseph Genden

Jeffrey Carl Brownscheidle

Maureen Anne Delaney

Robert Allen Cordes

Salma Ayub

Joshua W Bowman

Dhivya Jeganathan

Cliff Kucharski

Albert James Van Norstrand, Jr

Jentje Leenstra

Salim Ahmed Shah

Elizabeth A McGlone

James Wilson Bishop

Marcy Evelyn Byers

Jing Zhang

Maarten Jakob Boersma

Tu-An T Nguyen

Eula A Tolentino

Thao T Doan

Rokesh Jayasundar

Bernard Charles Drerup

Bryan J Lloyd

Phillip G Williams

Sheldon Bernard Levenstein

Steven J Battle

Naresh Nayar

Randal Craig Swanberg

Christopher Michael Abernathy

Christian Zoellin

Mark Anthony Check

Kurt Alan Feiste

Tilman Gloekler

Mary Douglass Brown

David Scott Ray

Michael Klaus Kroener

Michael Grassi

Niels Fricke

Benjamin W Stolt

Johannes Koesters

Parag Birmiwal

David S Walder

Maureen Terese Davis

Jerry Y Lu

Nasrin Sultana

Josh Bowman

Jose Eduardo Moreira

Richard James Eickemeyer

Cathy May

Hien Le

Tony Emile Sawan

Kenneth Lundy Ward

Shih-Hsiung Stephen Tung

Miles Robert Dooley

John Barry Griswell, Jr

George W Rohrbaugh, Iii

Kirk Edward Morrow

Richard Nicholas Iachetta, Jr

Yoanna Baumgartner

Jessica Hui-Chun Tseng

Jennifer L Molnar

Christian Gerhard Zoellin

Anh Tran Vinh

Olga Buchonina

Trac Minh Vu

Sudhi Ranjan Proch

An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries

Technology for fusing certain load instructions and compare-immediate instructions in a computer processor having a load-store architecture with respect to transferring data between memory and registers of the computer processor. In some embodiments the load and compare-immediate instructions are consecutive. In some embodiments, the instructions are only merged if: (i) the respective RA and RT fields of the two instructions match; (ii) the immediate field of the compare-immediate instruction has a certain value, or falls within a range of certain values; and/or (iii) the instructions are received in a consecutive manner.

Microprocessor that fuses load and compare instructions

Technology for fusing an add-immediate instruction with a load-immediate instruction (or store-immediate instruction) in a microprocessor. This can result in quicker address generation while performing a load and store operation.

Fusion to enhance early address generation of load instructions in a microprocessor

In an approach for decreasing a rate of logic voltage level transitions in a multiplexor, one of a plurality of inputs to a multiplexor is selected with a first multiplexor select value at a first clock, wherein each input to the multiplexor is identified as one of i) valid and ii) invalid and the first multiplexor select value is latched in a latch until the first multiplexor select value is replaced by a second multiplexor select value. The second multiplexor select value is determined. The second multiplexor select value is applied to the multiplexor at a second clock if and only if the second multiplexor select value is different from the first multiplexor select value and the second multiplexor select value selects a valid input, wherein the second clock follows the first clock. Subsequent to applying the second multiplexor select value, the second multiplexor value is latched in the latch.

Energy efficient source operand issue

Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level transfer of an execution thread between execution slices. Operation of such a multi-slice processor includes responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon execution of the plurality of instructions from the thread switching instruction generator, the execution thread from the first execution slice to the second execution slice.

Operation of a multi-slice processor implementing a hardware level transfer of an execution thread

Processor instruction scheduling by: providing a set of program instructions, selecting instructions for reordering from the set of program instructions, reordering the instructions according to instruction properties, assigning sequential instruction tags to the instructions, tagging the instructions for completion as a group in a completion table; and executing the instructions.

Program instruction scheduling

Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.

Fast multi-width instruction issue in parallel slice processor

Techniques are disclosed for performing issue queue snooping for an asynchronous flush and restore of a history buffer (HB) in a processing unit. One technique includes identifying an entry of the HB to restore to a register file in the processing unit. A restore ITAG of the HB entry is sent to the register file via a first restore bus, and restore data of the HB entry and the restore ITAG is sent to the register file via a second restore bus. After the restore ITAG and restore data are sent, an instruction is dispatched before the register file obtains the restore data. After it is determined that the restore data is still available via the second restore bus, a snooping operation is performed to obtain the restore data from the second restore bus for the dispatched instruction.

Issue queue snooping for asynchronous flush and restore of distributed history buffer

Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

Handling unaligned load operations in a multi-slice computer processor

Embodiments herein describe a reservation station (RS) in a processor that merges control data from multiple sources into a merged control data value. Before an instruction issues, the RS gathers and saves control data indicating how the instruction is to be executed. This control data may be saved in control registers. An instruction, however, can update many different types of status control bits in these registers. As such, the RS may store different types of control data for an instruction. Instead of the RS containing multiple registers and data paths for every type of control data, the embodiments herein describe merge logic in the RS that permits control data from different sources to be merged into a single control data value. Once the instruction is issued, the RS passes the merged control data value to an execution unit for processing.

Merging status and control data in a reservation station

A computer processing system is provided. The computer processing system includes a processor configured to insert a move instruction in an instruction scheduling dependency graph generated for operands of the instruction operating on register pairs to ensure operand readiness for all of the operands used by the instruction operating on register pairs.

Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core

Growing community of inventors

Austin, TX, United States of America

Sundeep Chadha