Sun Microsystems, Inc.

Intel Corporation

Sundari S Mitra

Philip Arnold Ferolito

Aleksandar Pance

Gregory Scott Mathews

David J Greenhill

Edward S Zager

Brad Heaney

Marc Elliot Levitt

Prasad H Chalasani

A control block clock distribution network includes a logic circuit, one or more nth-level buffers, and a (n-1)th-level buffer that drives the one or more nth-level buffers. The logic circuit includes a predefined area containing substantially only clocked logic elements. The number of clocked logic elements in the predefined area is constrained to be less than or equal to a predetermined maximum number. The one or more nth-level buffers are located within the predefined area, whereas the (n-1)th-level buffer is located outside of the predefined area. Each nth-level buffer receives the clock signal outputted by the (n-1)th-level buffer and provides a clock signal to a predetermined number of the clocked logic elements within the predefined area Because the predefined area has known dimensions, the length of the clock line from the (n-1)th buffer to the nth-level buffers is known to within a range. Additionally, the number of clocked logic elements and the number of nth-level buffers are known to within a range. Thus, the range of resistive-capacitive loading to each clocked element within the predefined area is known. Accordingly, the maximum clock skew between clocked logic elements within the predefined area can be determined. The maximum clock skew of the predefined area can be adjusted to a desired value by varying one or more of the dimensions of the predefined area, the range of nth-level buffers that can be placed in the predefined area, or the range of clocked logic elements that can be driven by each nth-level buffer.

Reduced skew control block clock distribution network

An interconnect structure includes in a first layer a clock line and a ground line running substantially parallel to the clock line, and a plurality of conductive regions lying in a second layer parallel to the first layer. The ground line is coupled to a source of ground potential. The conductive regions are aligned with the clock line and are disposed around a signal line routed in the second layer across the clock line. The conductive regions are electrically connected to the ground line, thereby forming a shield for the clock line that helps prevent clock signals propagated on the clock line from electromagnetically coupling with other signal lines. In one embodiment, a clock distribution network includes conductive regions (501, 503, 505 . . . ) in the metal layer below the clock line layer and two parallel ground lines (201, 203) in the same metal layer as the clock line (101). The conductive regions (501, 503, 505 . . . ) are electrically connected to the ground lines (201, 203) with vias (603A, 603B, 605A, 605B . . . ). In the same metal layer as the conductive regions, conductive signal lines (509, 511) are routed between the regions (501, 503, 505, 507 . . . ) to cross below the clock line. The conductive regions (501, 503, 505, 507 . . . ) form a shield between the clock line (101) and any signal lines (105) routed in the next metal layer adjacent to the metal layer containing the conductive regions.

Clock distribution network with efficient shielding

An interconnect structure includes in a first layer a clock line and a ground line running substantially parallel to the clock line, and a plurality of conductive regions lying in a second layer parallel to the first layer. The ground line is coupled to a source of ground potential. The conductive regions are aligned with the clock line and are disposed around a signal line routed in the second layer across the clock line. The conductive regions are electrically connected to the ground line, thereby forming a shield for the clock line that helps prevent clock signals propagated on the clock line from electromagnetically coupling with other signal lines. In one embodiment, a clock distribution network includes conductive regions (501, 503, 505. . . ) in the metal layer below the clock line layer and two parallel ground lines (201, 203) in the same metal layer as the clock line (101). The conductive regions (501, 503, 505 . . .) are electrically connected to the ground lines (201, 203) with vias (603A, 603B, 605A, 605B . . . ). In the same metal layer as the conductive regions, conductive signal lines (509, 511) are routed between the regions (501, 503, 505, 507. . . ) to cross below the clock line. The conductive regions (501, 503, 505, 507. . . ) form a shield between the clock line (101) and any signal lines (105) routed in the next metal layer adjacent to the metal layer containing the conductive regions.

A n level clock distribution network for a datapath block includes an external buffer that outputs a clock signal and a datapath block having a logic block and a buffer block containing one or more nth-level buffers implemented with predefined modular buffers. The logic block includes one or more predefined areas containing clocked logic elements. The number of clocked logic elements in a predefined area is constrained to be less than or equal to a predetermined maximum number. Each nth-level buffer receives the clock signal outputted by the external buffer and distributes this clock signal to the clocked logic elements within a corresponding predefined area of the logic block. The nth-level buffer driving each predefined area is implemented by selecting one or more buffers from a family of predefined modular buffers appropriate for the number of clocked logic elements in the predefined area. In cases where more than one predefined modular buffer is selected, the selected predefined modular buffers are connected in parallel. Because a family of predefined modular buffers is used instead of custom buffers, the design of the buffer block is greatly simplified. Moreover, this network is easily implemented with an automated place and route design tool by predefining each modular buffer in a standard cell library of the automated place and route design tool.

Clock distribution network with modular buffers

A final stage clock buffer for use in a clock distribution network in a circuit with scan design includes a demultiplexer circuit and a control circuit. The buffer receives an input clock signal and outputs a clock signal and a scan clock signal. The buffer can operate in a functional mode, a scan mode and a hold mode. The demultiplexer circuit receives the input clock signal and a scan enable signal. The scan enable signal, when asserted, causes the buffer to enter the scan mode. In the scan mode, the demultiplexer circuit propagates the input clock signal to a scan clock terminal and a constant logic level to a clock terminal. When the scan enable signal is deasserted, the demultiplexer circuit propagates the input clock signal to the clock terminal and a constant logic level to the scan clock terminal. The control circuit receives a chip-enable signal. When the chip-enable signal is asserted while the scan signal is deasserted, the buffer enters the functional mode. The asserted chip-enable signal causes the control circuit to allow the input clock signal to continue to propagate to the clock terminal. When both the chip-enable signal and the scan signal are deasserted, the buffer enters the hold mode. The deasserted chip-enable signal causes the control circuit to stop the propagation of the input clock signal to the clock output terminal and, instead, causes the clock signal to remain in a constant logic state.

Final stage clock buffer in a clock distribution network

A flip-flop with scan capability includes a four switches, a master stage, a slave stage and a scan-out logic gate. The flip-flop can operate in a functional mode, and a scan mode and receives a clock signal, a data signal, a scan clock signal and a scan-in signal. The flip-flop enters the functional mode when the clock signal runs free and the scan clock signal is held constant. The first switch receives the data signal and provides the data signal to the master stage for storage during a first part of a clock cycle. During a second part of the clock cycle, the third switch, connected between the master stage and the slave stage, closes, providing the data stored in the master stage to the slave stage and outputted as a q output signal. The flip-flop enters the scan mode when the clock signal is held constant and the scan clock signal runs free. The first switch is controlled to stay open by the constant clock signal. During a first part of a scan clock cycle, the second switch closes, providing the scan-in signal to the master stage. The data stored in the master stage is provided to the fourth switch, connected between the master stage and the scan-out logic gate. During a second part of the scan clock cycle, the fourth switch closes, providing the data stored in the master stage to the scan-out logic gate, which outputs a scan-out signal.

Flip-flop with full scan capability

A variable frequency clock generator provides complementary phase clock signals for a microprocessor at a selectable one of a plurality of frequencies. The outputs may be dynamically switched between any of the frequencies so that every cycle of the phase clock signals has a duration at least as great as the cycle duration of the highest frequency.

An apparatus for providing a clock signal for a microprocessor at a

A clock switching apparatus is provided in a data processing system which includes a system clock for selectively switching the system clock from a first clock signal to a second clock signal and vice versa. The clock switching apparatus includes a multiplexer coupled to receive the first clock signal and the second clock signal for selectively switching the system clock from the first clock signal to the second clock signal. The multiplexer provides the system clock. A control logic circuit is coupled to receive the second clock signal and a control signal for controlling the multiplexer to switch the system clock from the first clock signal to the second clock signal, wherein the control signal is synchronized to the second clock signal in the control logic circuit to become a synchronized control signal. The multiplexer switches the system clock from the first clock signal to the second clock signal when receiving the synchronized control signal from the control logic circuit. A pass logic circuit is provided for outputting the system clock. The pass logic circuit receives the system clock from the multiplexer. The pass logic circuit is controlled by the control logic circuit to output the system clock such that a glitch-free and minimum transitional period within which the system clock is switched from the first clock signal to the second clock signal is ensured. A method of selectively switching the system clock from the first clock signal to the second clock signal in the data processing system is also described.

Clock switching apparatus and method for computer systems

Timing signals governing the precharge and evaluation phases of a PLA are generated by internal circuitry so that the PLA can be maintained in a fully static mode without destroying data integrity and without dissipating a significant amount of power. 'Dummy' lines connected at every programmable intersection are added to the PLA to provide a measure of the maximum propagation delay. The evaluation phase of the PLA is terminated closely following the maximum propagation delay and precharging is begun soon thereafter. The timing ensures that evaluation completes, valid data is latched and the PLA is returned to a precharge condition even if the phase clock signals are suspended and regardless of the states of the phase clock signals when suspended.

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Milpitas, CA, United States of America

Sundari S Mitra