Nxp B.v.

Sundaravaradan Rangarajan

Rajendra Kumar

Johannes Boonstra

A FIFO memory circuit is for interfacing between circuits with different clock domains. The circuit has a FIFO memory (), a write pointer circuit () clocked by the clock of a first clock domain and controlling the memory location to which data is written, and a read pointer circuit clocked by the clock of a second clock domain and controlling the memory location from which data is read. The read and write pointer circuits use gray coding. The memory circuit further comprises a duplicate write pointer circuit () which has its write pointer address incremented synchronously with the write pointer circuit (), and which has a starting write address selected such that the duplicate write pointer address lags behind the write pointer address circuit by a number of address locations corresponding to the size of the FIFO memory (). A comparator () compares the read pointer circuit address with the duplicate write pointer circuit address for determining a full status of the FIFO memory.

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Bengaluru, India

Sundaravaradan Rangarajan