Intel Corporation

Sundar Ramani

Arvind Mandhani

Ashish V Choubal

Ajaya V Durg

Kalyan Muthukumar

Arvind Raman

Samudyatha Chakki

Vinu K Elias

Arvind S Tomar

Jianjun Liu

Olivia Wu

Jason Seung-Min Kim

Nitin N Garegrat

Andrew Yang

Yogesh Bansal

Tom Schebye

Mayank Kaushik

Mrinal Iyer

Embodiments include an apparatus comprising an execution unit coupled to a memory, a microcode controller, and a hardware controller. The microcode controller is to identify a global power and performance hint in an instruction stream that includes first and second instruction phases to be executed in parallel, identify a local hint based on synchronization dependence in the first instruction phase, and use the first local hint to balance power consumption between the execution unit and the memory during parallel executions of the first and second instruction phases. The hardware controller is to use the global hint to determine an appropriate voltage level of a compute voltage and a frequency of a compute clock signal for the execution unit during the parallel executions of the first and second instruction phases. The first local hint includes a processing rate for the first instruction phase or an indication of the processing rate.

Software assisted power management

In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

Selecting a low power state based on cache flush latency determination

In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.

Autonomously controlling a buffer of a processor

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Bengaluru, India

Sundar Ramani