International Business Machines Corporation

Kulicke & Soffa Holdings, Inc.

Sundar M Kamath

Benjamin V Fasano

Richard Francis Indyk

Scott Ira Langenthal

Solomon I Beilin

Srinivasa S Reddy

David J Chazan

Jeffrey Allen Zitz

Frank Louis Pompeo

Rao Venkateswara Vallabhaneni

Kenneth Charles Marston

Patrick Anthony Coico

Srinivasa S N Reddy

Daniel P O'Connor

James H Covell

Ronald L Hering

Jan I Strandberg

David H Gabriels

Karl Joseph Puttlitz

Lewis S Goldman

John Ulrich Knickerbocker

Rajesh Bhikhubhai Patel

Lewis Sigmund Goldmann

Herbert I Stoller

Ajay Prabhakar Giri

Paul Robert Walling

Lisa M Studzinski

An integrated circuit module, a land grid array module, and a method for forming the module, include a substrate, which mounts one or more chips or discrete electronic components, and a cap for covering the substrate, and including at least one protrusion coupled to the cap for limiting the amount of flexing of the substrate during actuation. The at least one protrusion can be either rigidly fixed to the cap or adjustably inserted through the cap.

Stress resistant land grid array (LGA) module and method of forming the same

A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.

Isolated flip chip of BGA to minimize interconnect stress due to thermal mismatch

A wiring substrate with reduced thermal expansion. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or a BGA package. The wiring substrate has a thermal expansion reduction insert in a thermal expansion stress region where the integrated circuit is mounted. The thermal expansion reduction insert may extend a selected distance from the edge or edges of the integrated circuit attachment area, or stop a selected distance from the edge or edges of the integrated circuit attachment area, or be essentially equal to the integrated circuit attachment area. The thermal expansion reduction insert reduces the thermal expansion of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In a specific embodiment, the wiring substrate is a laminated printed wiring board with the thermal expansion reduction insert in a layer next to an outer layer to which the integrated circuit is joined (mounted). In a further embodiment the thermal stress reduction insert is a CIC insert or a copper-molybdenum insert. In an alternative embodiment, the wiring substrate is a thin film substrate or a VLSI substrate.

Wiring substrate with thermal insert

Disclosed is a multilayer ceramic substrate having an outer pad, for example an I/O pad, which is anchored to a middle pad of the multilayer ceramic substrate by a plurality of vias which in turn is anchored to an inner pad of the multilayer ceramic substrate by a second plurality of vias. The middle and outer pads and vias are made of high metal material, preferably 100% metal, so they won't adhere very well to the ceramic substrate. The inner pad is a composite metal/ceramic material which will bond very well to the ceramic substrate.

Multilayer ceramic substrate with anchored pad

Isolated flip chip or BGA to minimize interconnect stress due to thermal mismatch

A high performance TF-ceramic module for mounting integrated circuit chips thereto and a method of fabricating the module at reduced cost. The substrate includes thin film (TF) layers formed directly on a layered ceramic base. A first thick film wiring layer is formed on or embedded in a top surface of the thick film layered ceramic base using thick film techniques. A first dielectric layer of a polyimide or other organic material, or an insulating material different than the ceramic material is formed on top of the first wiring layer. The dielectric layer may be spun on or sprayed on and baked; vapor deposited; laminated to the ceramic base; or an inorganic layer may be deposited using plasma enhanced chemical vapor deposition (PECVD). Vias are formed through the first dielectric layer. A second wiring layer is formed on the first dielectric layer. A second dielectric layer is formed on the second wiring layer. At least one mounting location suitable for mounting an electronic component is formed on the second dielectric layer. The substrate may be attached a printed circuit board by direct attachment, pin grid array (PGA), land grid array (LGA), ball grid array (BGA), column grid array (CGA) and miniBGA on the bottom layer of the ceramic base.

Direct deposit thin film single/multi chip module

Multilayer glass ceramic substrate electronic components having enhanced flexibility and strength are prepared using greensheets as a top and/or bottom layer, which greensheets are made from a glass-ceramic greensheet casting composition comprising crystallizable glass, a binder resin and a solvent system, and preferably a plasticizer. The top and/or bottom greensheets have a lower coefficient of thermal expansion (CTE) than the greensheets used to make the internal layers of the MLC and both greensheets are characterized by having, after sintering, a microstructure which is greater than 99% crystalline. A crystalline matrix forming material such as P,O,is preferably used in the composition. This type structure, in combination with the lower CTE, has been found to provide an MLC having enhanced strength and flexibility.

Method and materials for increasing the strength of crystalline ceramic

Disclosed is a multilayer ceramic substrate having an outer pad, for example an I/O pad, which is anchored to an inner pad of the multilayer ceramic substrate by either a plurality of vias or one large via. The outer pad and vias are made of high metal material, preferably 100% metal, so they won't adhere very well to the ceramic substrate. The inner pad is a composite metal/ceramic material which will bond very well to the ceramic substrate.

A method for making multilayer ceramic substrates having substantially reduced planar shrinkage and distortion resulting from the firing or sintering process. Contact sheets are employed in the fabrication process on the surface of the multilayer ceramic substrate to be fired with the contact sheets being prepared from a composition containing a non-sinterable non-metallic inorganic material such as alumina having an average particle size approximately about 1 micron or less and an organic binder and preferably a plasticizer. In a preferred embodiment of the invention, the multilayer structure to be fired containing the contact sheet of the invention is provided with a beveled or chamfered edge at an angle of greater than about 60 degrees. A fabrication process employing only chamfering of the edge or the use of a contact sheet of the invention also provides improved multilayer ceramic substrate products. A further feature is a method to control the surface topography of surface metallization by adjusting the compressibility of the contact sheets during fabrication of the substrate.

Method for producing ceramic surfaces with easily removable contact

Disclosed is a multilayer ceramic substrate, and a method for forming same, which has an outer unsealed layer having a metallic via, an inner sealed layer having a composite via of metallic and ceramic materials and a further unsealed layer having a metallic via.

Ceramic substrate having a sealed layer

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San Jose, CA, United States of America

Sundar M Kamath