Other

International Business Machines Corporation

Sundar Kumar Iyer

Subramanian Srikanteswara Iyer

Chandrasekharan Kothandaraman

Axel Christoph Brintzinger

Ying Di Zhang

Herbert Lei Ho

Babar Ali Khan

Bomy A Chen

Chandrasekhar Narayan

Rama Divakaruni

Nivo Rovedo

Edward P Maciejewski

Satya N Chakravarti

George E Smith, Iii

Chandrasekara Kothandaraman

Hsing-Jen C Wann

Peter I Smeys

Michael Stetter

Frank Grellner

Alexander W Hirsch

Mark E Anderson, Ii

Chandcasekhar Narayan

An identification circuit for establishing and sensing the state of a fusible element used in on chip identification of the chip's type comprising: a circuit establishing control signals for turning the identification circuit on and off; dual paths energized by the control signals generated by the level setting circuit to energize one path through the fusible element to provide a state level and the other path through a reference path which provides a reference voltage level which is distinguishable from both the blown and unblown states of the fusible element; a differential sensing circuit for comparing the reference voltage level to the state level to provide a signal indicating the state of the fusible element; and protection circuitry to protect the circuit during an operation in which the state of the fusible element is set.

Circuits associated with fusible elements for establishing and detecting of the states of those elements

A fuse for semiconductor devices, in accordance with the present invention, includes a cathode formed from a first material, an anode formed from a second material and a fuse link connecting the cathode and the anode and formed from the second material. The second material is more susceptible to material migration than the first material when the fuse is electrically active such that material migration is enhanced in the second material.

Electrical fuses for semiconductor devices

An improved fuse structure in an integrated circuit (IC) structure is made by forming a gate stack comprised of layers of polysilicon and a silicide. Subsequent to the formation of the silicide layer, an etch stop silicon nitride layer is deposited over the silicide layer. The silicon nitride layer is patterned to expose the silicide layer. A soft passivation layer is deposited over the exposed silicide layer. The soft passivation layer has a low thermal conductivity which confines energy in the silicide layer, minimizing the current needed to program the fuse. The inherent ductility of the soft passivation layer prevents the generation of cracks in the surrounding layers.

Method and structure to reduce the damage associated with programming electrical fuses

A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Patterned buried insulator

Described herein is a fuse incorporating a covering layer disposed on a conductive layer, which is disposed on a polysilicon layer. The covering layer preferably comprises a relatively inert material, such as a nitride etchant barrier. The covering layer preferably has a region of relatively less-inert filler material. Upon programming of the fuse, the conductive layer, which can be a silicide, preferentially degrades in the region underlying the filler material of the covering layer. This preferential degradation results in a predictable &ldquo;blowing&rdquo; of the fuse in the fuse region underlying the filler material. Since the &ldquo;blow&rdquo; area is predictable, damage to adjacent structures can be minimized or eliminated.

Enhanced efuses by the local degradation of the fuse link

A method of connecting a trench capacitor in a dynamic random access memory (DRAM) cell. First, trenches are formed in a silicon substrate using a masking layer including a pad nitride layer on a pad oxide layer. Trench capacitors are formed in the trenches. A buried strap is formed in each trench on the capacitor. The nitride pad layer is pulled back from the trench openings, exposing the pad oxide layer and any strap material that may have replaced the pad oxide layer around the trenches. The straps and trench sidewalls are doped to form a resistive connection. During a subsequent shallow trench isolation (STI) process, which involves an oxidation step, the exposed strap material on the surface of the silicon surface layer forms oxide unrestrained by pad nitride without stressing the silicon substrate.

Method of forming a trench capacitor DRAM cell

A test structure and method for determining DRAM cell leakage. The cell leakage test structure includes a pair of buried strap test structures. Each buried strap test structure includes multiple trench capacitors formed in a silicon body. Each trench capacitor is connected to a trench sidewall diffusion by at least one buried strap. An n-well ring surrounds each buried strap test structure and divides the buried strap test structure into two separate array p-wells, one being a contact area and the other a leakage test area. The contact area includes contacts to the trench capacitor plates for the corresponding buried strap test structure. In one buried strap test structure, a layer of polysilicon, essentially covers the trench capacitors in the leakage test area to block source/drain region formation there. The other of the two buried strap test structures includes polysilicon lines simulating wordlines with source and drain regions form on either side. A buried n-band contacts the n-well rings, essentially forming an isolation tub around each array well. Cell leakage is measured by measuring leakage current in each buried strap test structure, individually, and then extracting individual leakage components from the measured result.

DRAM cell buried strap leakage measurement structure and method

A fuse for semiconductor devices, in accordance with the present invention, includes a cathode including a first dopant type, and an anode including a second dopant type where the second dopant type is opposite the first dopant type. A fuse link connects the cathode and the anode and includes the second dopant type. The fuse link and the cathode form a junction therebetween, and the junction is configured to be reverse biased relative to a cathode potential and an anode potential. A conductive layer is formed across the junction such that current flowing at the junction is diverted into the conductive layer to enhance material migration to program the fuse.

Electrical fuses employing reverse biasing to enhance programming

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Beacon, NY, United States of America

Sundar Kumar Iyer