Samsung Electronics Co., Ltd.

Sunchul Kim

Pyoungwan Kim

Hyunki Kim

Taehun Kim

Juhyeon Oh

Jinkyeong Seol

Byoung Wook Jang

Su-Min Park

Kyungsuk Oh

Junwoo Park

Inku Kang

Heeyeol Kim

Chanhee Jeong

Sang-Uk Kim

Juhyung Lee

Seok Geun Ahn

Soohwan Lee

A semiconductor package includes a first substrate, a second substrate provided on the first substrate, a semiconductor chip provided between the first substrate and the second substrate, solder structures extending between the first substrate and the second substrate and spaced apart from the semiconductor chip, and bumps provided between the semiconductor chip and the second substrate. The solder structures electrically connect the first substrate and the second substrate.

Semiconductor package

A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed.

A semiconductor package includes a first substrate including a first recess formed in a top surface of the first substrate, a first semiconductor chip disposed in the first recess and mounted on the first substrate, an interposer substrate disposed on the first semiconductor chip and including a second recess formed in a bottom surface of the interposer substrate, an adhesive layer disposed in the second recess and in contact with a top surface of the first semiconductor chip, a plurality of connection terminals spaced apart from the first recess and connecting the first substrate to the interposer substrate, and a molding layer disposed between the first substrate and the interposer substrate.

Semiconductor package and method of fabricating the same

A semiconductor package includes a package substrate, a first semiconductor chip disposed on the package substrate, at least one second semiconductor chip disposed on a region of an upper surface of the first semiconductor chip, a heat dissipation member disposed in another region of the upper surface of the first semiconductor chip and at least a region of an upper surface of the second semiconductor chip, and having an upper surface in which at least one trench is formed, and a molding member covering the first semiconductor chip, the second semiconductor chip, an upper surface of the package substrate, and side surfaces of the heat dissipation member, and filling the at least one trench while exposing the upper surface of the heat dissipation member.

Semiconductor package having molding member and heat dissipation member

A packaged semiconductor device includes a package substrate, a first semiconductor device on the package substrate, and at least one second semiconductor device that extends on and partially covers the first semiconductor device. A heat dissipating insulation layer is provided as a coating on the first and second semiconductor devices. A conductive heat dissipation member is provided, which extends upwardly from the heat dissipating insulation layer and on portions of the first and second semiconductor devices. A protective member is provided on the package substrate, to cover the first and second semiconductor devices and the conductive heat dissipation member. This protective member includes a first covering portion, which covers an upper surface of the conductive heat dissipation member.

Packaged semiconductor devices having enhanced thermal transport and methods of manufacturing the same

A semiconductor package including a package substrate; a first semiconductor chip on the package substrate; a second semiconductor chip on an upper surface of the first semiconductor chip; an insulating layer on surfaces of the first semiconductor chip and the second semiconductor chip; a heat dissipation member on the insulating layer such that the heat dissipation member includes a region on an upper surface of the first semiconductor chip on which the second semiconductor chip is not disposed, and a region on an upper surface of the second semiconductor chip; a molding member on the package substrate and encapsulating the first semiconductor chip, the second semiconductor chip, and the heat dissipation member such that the molding member exposes at least a portion of an upper surface of the heat dissipation member; and a reinforcing member on the heat dissipation member and the molding member.

Semiconductor package including molding member, heat dissipation member, and reinforcing member

A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.

A semiconductor package and a method manufacturing the same are disclosed. At least one semiconductor chip is mounted on a package substrate. An insulative mold layer is formed at sides of the semiconductor chip having at least one recess in a region in which conductive connection members are formed, the recess defining one or more protrusions within the mold layer. An interposer is positioned on the protrusions with the conductive connection members connecting and providing electrical connections between conductive pads on the upper surface of the package and conductive pads on the lower surface of the package substrate. The protrusions may position the interposer in the vertical direction by defining the vertical spacing between the lower surface of the interposer and the upper surface of the package substrate. The protrusions may also position the interposer in one or more horizontal directions and/or prevent substantial movement during connecting of the interposer to the package substrate. An under-fill resin layer may be injected into remaining space between the interposer and the package substrate.

Semiconductor packages and methods of manufacturing same

A semiconductor package includes a first semiconductor chip on a first substrate, a first mold layer provided on the first substrate to cover a side surface of the first semiconductor chip, a solder structure provided on the first substrate, and a second substrate provided on the solder structure. A guide receptacle is formed at one of a top surface of the first mold layer and a bottom surface of the second substrate, a first alignment protrusion is formed at the other of the top surface of the first mold layer and the bottom surface of the second substrate, and at least a portion of the first alignment protrusion is provided in the guide receptacle.

Growing community of inventors

Hwaseong-si, South Korea

Sunchul Kim