Sharp Kabushiki Kaisha Corporation

Sunay Shah

Patrick Zebedee

Benjamin James Hadwen

Hajime Washio

Michael James Brownlow

Lesley Anne Parry-Jones

Allan Evans

Michael Paul Coulson

Stephen Day

Emmanuel Zyambo

Lloyd Lukama

Gareth Nicholas

Olivier Karim Abed-meraim

A charge storage circuit for a pixel comprises a charge storage node. First and second series-connected transistors () are provided for selectively isolating the charge storage node from a first voltage input (,SL) for supplying a data voltage. The circuit is provided with a voltage follower circuit for replicating a voltage at the charge storage node () at another node in the circuit thereby to reduce the drain-source voltage across the second transistor (). The first transistor forms part of the voltage follower circuit.

Charge storage circuit for a pixel, and a display

An ambient light sensor includes a first stack of at least two photodiodes, wherein a cathode of one of the at least two photodiodes is electrically connected to an anode of another of the at least two photodiodes. The ALS further includes a bias source for providing a bias voltage to the first stack, and at least one switch electrically connected to the first stack. The at least one switch is operative to periodically apply the bias voltage to and remove the bias voltage from the first diode stack.

Apparatus and method for preventing charge pumping in series connected diode stacks

A display device includes a first layer having an optically active display portion, a second layer including a photovoltaic element, and a third layer including electronics operatively coupled to the first layer, wherein the electronics are configured to drive the optically active display portion. Further, the second layer is arranged between the first and third layers.

Integrated display and photovoltaic element

A programmable read-only memory comprises a memory cell or a plurality of such cells arranged as an array. Each memory cell comprises a transistor, such as a MOS TFT. An electronic switch allows the control electrode, such as the gate, to be substantially electrically isolated during a programming mode so that the gate is electrically floating during this mode. During the programming mode, a programming voltage is supplied across the main conductive path of the transistor, such as across the source-drain channel. The programming voltage is sufficiently large to fuse the main conduction path when the control electrode of the transistor is floating but is insufficient to fuse the main conduction path when the control electrode is not floating and is connected to a suitable defined voltage. The transistor therefore performs functions of memory cell selection while simultaneously acting as the fusible element and the arrangement requires fewer transistors which are capable of operating at the programming current required for fusing. The memory may therefore occupy a reduced area.

Programmable read-only memory

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Oxford, United Kingdom

Sunay Shah