Kabushiki Kaisha Toshiba

Sunao Ogawa

Yasuo Yamada

Akira Nishimura

Akira Kanuma

A single chip microcomputer comprises a central processing unit (CPU),a on-chip RAM,a on-chip ROM,a first bus DBUS for connecting the CPU, RAM, and ROM with one another and transferring data between them, a second bus ABUS for passing address data corresponding to the data passed through the first bus, a third bus SDBUS for connecting the CPU,with the RAM,and transferring data between them, the number of bits of the third bus SDBUS being larger than that of the first bus DBUS, and a fourth bus BABUS for connecting the CPU,with the RAM,and passing address data corresponding to the data passed through the third bus SDBUS. The CPU,has a data memory RF serving as general purpose registers for providing internal data to the third bus SDBUS, and a bank specifying register BP for holding positional data of a mapping region in the RAM,where the contents of the data memory RF are mapped and providing the positional data to the fourth bus BABUS. The RAM,has a memory cell array,a bank address control circuit,connected to the fourth bus BABUS, for generating a real address according to the contents of the bank specifying register BP (BP,, BP,), and a selection circuit,for selecting the real address generated by the bank address control circuit,or the address provided through the second bus ABUS.

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Kawasaki, Japan

Sunao Ogawa