Sharp Kabushiki Kaisha Corporation

Sunao Etoh

Yasuhiro Matsushima

Yutaka Takafuji

Hisao Okada

A liquid crystal display device according to the present invention includes an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, and a vertical drive circuit for driving the active matrix array, in which the vertical drive circuit includes: scanning circuits N in number (N being a positive integer), which receive a start pulse and output pulse signals, the respective scanning circuits sequentially shifting the pulse signal by one-half of a clock signal cycle each; AND gate circuits N&times;M in number (M being an integer no less than 2), each provided with a first control terminal and a second control terminal, every M adjacent AND gate circuits being connected together via the first control terminals thereof, which receive a signal from one of the N scanning circuits, and every Mth AND gate circuit being connected together via the second control terminals thereof, which receive one of M kinds of second control signal; and NAND gate circuits, each of which receives an output from one of the AND gate circuits and one of two kinds of third control signal outputted by a third control terminal.

LCD driving circuitry with reduced number of control signals

A liquid crystal display device includes a liquid crystal between a substrate having gate buslines, source buslines, switching elements, pixel electrode array, gate driver, source driver, etc., and a substrate having a counter electrode, etc. In this liquid crystal display device, the gate driver performs simultaneous two-line scanning by applying a scanning signal to two gate buslines simultaneously. The source driver feeds video signals of opposite polarities to adjacent source buslines, respectively. The video signals are inverted every vertical scanning period.

Liquid crystal display device

The driving circuit of this invention for a display device displaying a plurality of gray levels in accordance with digital data including a first bit portion and a second bit portion, includes: a voltage dividing circuit for generating a plurality of interpolation voltages between a plurality of gray level voltages supplied externally by dividing the plurality of gray level voltages; a first selection circuit for selecting a first voltage and a second voltage which is different from the first voltage among the plurality of gray level voltages and the plurality of interpolation voltages based on the first bit portion of the digital data; a second selection circuit for selecting one of a plurality of oscillating signals having different duty ratios based on the second bit portion of the digital data; and an output circuit for outputting an oscillating voltage which oscillates between the first voltage and the second voltage selected by the first selection circuit at a duty ratio of the oscillating signal selected by the second selection circuit.

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Tenri, Japan

Sunao Etoh