Xilinx, Inc.

Sunae Kang

Derek R Curd

Ronald J Mack

Michael J Dibish

Rafael G San Luis, Jr

A tester to device-under-test interface is disclosed in which a PCB has a socket for a device under test (DUT), one or more cable connectors for cables from an IC tester, an interface matrix card slot having a plurality of contacts electrically connected to the DUT socket and the cable connector pins, and an interface matrix card having a plurality of horizontal and vertical conductors capable of being electrically connected to each other for mapping the proper connection of signals between the DUT socket and the tester cables.

Load board with matrix card for interfacing to test device

A novel test procedure is used to determine the optimum programmable charge pump levels for a flash memory array in a CPLD. According to the method of the invention, an automated tester steps through all combinations of charge pump codes and attempts to program the flash memory with each combination of voltage levels. For each combination, the results of the test (pass or fail) are logged and stored into a map or array. The center of a window of passing pump codes is taken as the starting reference point. The next step is to verify the actual voltage level associated with the pump code combination corresponding to the starting reference point. The reference pump code is loaded into the device and the corresponding flash memory cell voltage levels are measured. If the measured voltage level does not fall into the preferred range, the tester automatically adjusts the level towards the preferred range by adjusting the pump codes.

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Los Gatos, CA, United States of America

Sunae Kang