Hynix Semiconductor Inc.

Sun Woo Hwang

Soo Hyun Kim

Young Jin Lee

Baek Mann Kim

Dong Ha Jung

Jeong Tae Kim

Kwan Yong Lim

Noh Jung Kwak

A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuOlayer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuOlayer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

Metal wire for a semiconductor device formed with a metal layer without voids therein and a method for forming the same

A tungsten polymetal gate is made by forming a gate insulation layer and a polysilicon layer on a semiconductor substrate; depositing a barrier layer on the polysilicon layer; depositing a tungsten nucleation layer on the barrier layer through an ALD process; depositing a tungsten layer on the tungsten nucleation layer through a CVD process; depositing a hard mask layer on the tungsten layer; and etching the hard mask layer, the tungsten layer, the tungsten nucleation layer, the barrier layer, the polysilicon layer, and the gate insulation layer.

Method of forming tungsten polymetal gate having low resistance

A semiconductor memory device is manufactured by: forming a hole by etching an interlayer insulation film formed over a semiconductor substrate; forming a barrier film over the interlayer insulation film including a surface of the hole; forming a first metal film over the barrier film so as to fill in the hole; forming a bit line contact plug in the hole by removing the first metal film and the barrier film so as to expose the interlayer insulation film; carrying out a gas treatment to a surface of the interlayer insulation film including the bit line contact plug so as to promote a growth of metal nucleation; forming a second metal film over the gas treated interlayer insulation film; and forming a bit line in contact with the bit line contact plug by etching the second metal film.

Method for manufacturing semiconductor device capable of reducing parasitic bit line capacitance

Growing community of inventors

Kyoungki-do, South Korea

Sun Woo Hwang