Unitest Inc.

Sun Whan Kim

Sang Sig Lee

Jong Koo Kang

Dae Kyoung Kim

Dal Jo Lee

A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test selection command.

Sequential semiconductor device tester

A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test pattern data.

Disclosed herein is a semiconductor test apparatus for simultaneously testing a plurality of semiconductor devices. The semiconductor test apparatus includes a plurality of pattern generation boards, a DUT board, a backplane board, and a power supply unit.

Semiconductor test apparatus for simultaneously testing plurality of semiconductor devices

The present invention relates to a semiconductor test interface for interfacing a DUT (Device Under Test) to a pin card using a cable comprising a DUT board including one or more first connectors for electrically connecting one or more test sockets for mounting the DUT to the one or more cables, and a circuit wiring for electrically connecting the one or more test sockets to the one or more first connectors; and the one more cable including a second connector for an electrical connection to the one or more first connectors, and a third connector for an electrical connection to the pin card, wherein the one or more first connectors correspond to the one or more cables by 1:1. In accordance with the present invention, the manufacturing cost is reduced by simplifying the manufacturing process and the semiconductor test interface may easily correspond to the test of the different DUTs.

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Yongin-si, South Korea

Sun Whan Kim