Northern Telecom Limited

Sun-Shiu D Chan

Lawrence H Sasaki

Lorenzo L Longo

Thomas N Little

A scaler comprising a plurality of flip-flops, varies its frequency division to correct phase by 0.5 clock cycle. Each flip-flop is continuously and synchronously responsive to either a rising or a falling edge of the clock pulses. Normally, the scaler's state transits along one of two loops, which generate output pulses having identical repetition rates. When a control signal is applied, the scaler's state transits from one loop to the other, generating at least one output at an alternative repetition rate. The alternative repetition rate is either lower or higher than the identical repetition rate by an integral number of half cycles of the input clock pulses. Where there are two control signals, a lower or higher alternative repetition rate can be selected. Since the flip-flops are responsive to either edge of the clock pulses without clock gating interruptions, there is no jitter and the scaler's robustness is improved. Also the clock frequency can be effectively halved.

Scaler for synchronous digital clock

A CMOS integrated filter includes a passive network of resistive and capacitive paired elements and a first differential amplifier, for implementing a second order low pass filter function. A second amplifier is connected in voltage following configuration at an input of the first amplifier. A filter output is provided by an output of the second amplifier.

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Kanata, Canada

Sun-Shiu D Chan