Skhynix Inc.

Sun Ki Cho

Jun Ho Lee

Boo Ho Jung

Yang Hee Kim

Ic Su Oh

Hyun Seok Kim

Young Won Kim

Tae Yong Lee

Sung Woo Han

Hae Kang Jung

Yang Ho Sur

Chang Kyu Choi

Kyung Hoon Kim

Dae Han Kwon

Tae Jin Hwang

Eun Ji Choi

Soon Sung An

Jun Yong Song

Yong Suk Choi

Sung Hwa Ok

Keun Seon Ahn

Bon Kwang Koo

In Seok Kong

Dong Uc Ko

Jae Hyeong Hong

Jun Seo Jang

Dong Wook Jang

Heon Ki Kim

Gwan Woo Kim

Jung Yeop Lee

Beom Kyu Seo

Ji Young Lee

Sung Gil Jang

Min Sung Cheon

A voltage generation circuit includes a voltage generation unit configured to generate a reference voltage using a power supply voltage and output the reference voltage through a voltage output node. The voltage generation circuit also includes a pre-charge unit configured to drive the voltage output node using the power supply voltage in response to a pre-charge control signal. The voltage generation circuit further includes a pre-charge control unit configured to generate at least one sampling voltage using the power supply voltage and generate the pre-charge control signal according to a result obtained by comparing the at least one sampling voltage with the reference voltage.

Pre-charge control circuit and voltage generation circuit including the same

An oscillating signal generating circuit drives an oscillating signal to a first logic level based on a first control signal, which is generated by delaying the oscillating signal through a clock delaying circuit, and drives the oscillating signal to a second logic level based on a second control signal, which is generated by delaying the oscillating signal by a fixed delay amount.

Oscillating signal generating circuit and a semiconductor apparatus using the same

A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.

Buffer circuit

A receiving circuit may include an amplifier. The amplifier may include a first amplification circuit and a second amplification circuit. The first amplification circuit may be configured to differentially amplify a first input signal and a reference signal and configured to generate output signals. The second amplification circuit may be configured to differentially amplify a second input signal and the reference signal and configured to generate the output signals.

Amplifier, and receiving circuit, semiconductor apparatus, and system using the amplifier

An amplification circuit is provided. The amplification circuit may include an amplification stage configured to amplify a first signal and a second signal, and generate third and fourth signals while in a first operation period. The amplification circuit may include a latch stage configured to latch the third and fourth signals while in a in a second operation period. The amplification circuit may supply a low voltage to the amplification stage during the first operation period, the low voltage to the latch stage during the second operation period, a high voltage to the amplification stage during the first operation period, and the high voltage to the latch stage during the second operation period.

Amplification circuit, and frequency dividing circuit, semiconductor apparatus and semiconductor system including the amplification circuit and or frequency dividing circuit

A transmission circuit may be provided. The transmission circuit may include a strobe control circuit and an output driver. The strobe control circuit may generate strobe driving signals based on information and a clock signal. The output driver may generate a strobe signal by driving a signal transmission line. The transmission circuit may drive the signal transmission line to a specified level for a predetermined time after transmission of the strobe signal is completed.

Transmission circuit, and semiconductor apparatus and system using the same

A semiconductor apparatus may include a transmission circuit, a reception circuit, and a pad commonly coupled to the transmission circuit and the reception circuit. When either the transmission circuit or the reception circuit is activated, parasitic capacitance of a line coupled to the transmission circuit, the reception circuit, and the pad is varied.

Semiconductor apparatus reducing a parasitic capacitance

A semiconductor device may be provided. The semiconductor device may be configured to adjust a level of a first strobe signal to a predetermined level during a first time period. The semiconductor device may be configured to adjust a swing width of the first strobe signal during a second time period.

Semiconductor devices and semiconductor systems relating to the prevention of a potential difference between signals from being reversed

Provided is a semiconductor apparatus which includes a plurality of output buffers configured to connect a plurality of power sources, and a data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers based on the noise.

Method for reducing output data noise of semiconductor apparatus and semiconductor apparatus implementing the same

Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result.

Provided is an MCP including a plurality chips stacked therein. Each of the chips includes a plurality of inductor pads configured to transmit power or signals, and at both sides of a reference inductor pad, a first and a second inductor pads are formed to generate magnetic fluxes in different directions from each other.

Multi-chip package with improved signal transmission

A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of banks; a column control region disposed adjacent to at least one of sides of each bank which are perpendicular to an extending direction of the power lines; and a conductive plate disposed over the column control region and electrically connected to the plurality of power lines.

Semiconductor memory apparatus with power-meshed structure

A semiconductor integrated circuit includes a first voltage line to which a first ground voltage is applied, a second voltage line to which a second ground voltage is applied, a third voltage line to which a first power supply voltage is applied, and a coupling unit including a MOS transistor having a source coupled to the first voltage line, a drain coupled to the second voltage line, and a gate coupled to the third voltage line.

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Icheon-si, South Korea

Sun Ki Cho