Samsung Electronics Co., Ltd.

Korea Institute of Science and Technology

Sun-Il Shim

Jae-Hoon Jang

Hansoo Kim

Han-Soo Kim

Jaehun Jeong

Donghyuk Chae

Youngho Lim

Jae-Hun Jeong

Won-Seok Cho

Sung-Min Hwang

Ki-Hyun Kim

Jin-Ho Kim

Sung-Hoi Hur

Su-Youn Yi

Jung-Dal Choi

Won-Cheol Jeong

Kwang-soo Kim

Jae-Kwan Park

Hyun-Suk Kim

Chang-Seok Kang

Shin-Hwan Kang

Seung Jun Hyun

Sun-Jung Kim

Hae-min Lee

Yong-Tae Kim

Jinman Han

Byeong-In Choe

Seung-hyun Lim

Seong-Il Kim

Jin-Man Han

Seung-Hyun Lim

Chun-Keun Kim

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Nonvolatile memory devices, operating methods thereof and memory systems including the same

A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.

Semiconductor memory device

A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.

Vertical memory devices and methods of manufacturing the same

Non-volatile memory devices, operating methods thereof and memory systems including the same

A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.

Vertical non-volatile memory device and method of fabricating the same

Vertical non-volatile memory device including plural word line stacks

A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

Non-volatile memory device having vertical structure and method of operating the same

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Seoul, South Korea

Sun-Il Shim