Hynix Semiconductor Inc.

Sun-Hyuck Yon

Kee-Teok Park

A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.

Semiconductor memory device and operation method thereof

A delay apparatus for a delay locked loop includes a plurality of delay devices that are formed by modeling a plurality of signal processing structures through which a delay locked loop clock output from a delay locked loop reaches an output circuit of a semiconductor memory apparatus from an output terminal of the delay locked loop. At least one of the plurality of delay devices is composed of a variable delay device in which a delay time varies according to a change in operation voltage.

Growing community of inventors

Kyoungki-do, South Korea

Sun-Hyuck Yon