Samsung Electronics Co., Ltd.

Korea University Industry and Academy Corporation Foundation

Sun-Hee Park

Jin-Ho Kim

Yong-Hwan Kwon

Young-Il Kim

Hwan-Sik Lim

Moon-Gi Cho

Jeong-Woo Park

Young Lyong Kim

Yonghwan Kwon

Seung-Ki Chae

Pil-Kwon Jun

Pil-kwon Jun

Jeong Sheop Shin

Mi-Ae Kim

Moon Gi Cho

Jung Myung Bae

Shin-Chan Kang

Seol Ah Noh

Boin Noh

Ui-hyoung Lee

Jae-Seok Lee

Kyung Hee Paek

Man Sup Kwak

Kook-Joo Kim

Gyoung-Eun Byun

Moon-Chul Lee

Young-Tack Hong

Dong-Ha Shim

Kuang-Woo Nam

A bump structure may include a body portion spaced apart from a pad disposed on a substrate and a first extension extending from a side of the body portion onto the pad. A second extension extends from another side of the body portion.

Bump structures having an extension

An electrical interconnection can be provided using a bump stack including at least two solder bumps which are stacked on one another and at least one intermediate layer interposed between the at least stacked two solder bumps.

Semiconductor devices having stacked solder bumps with intervening metal layers to provide electrical interconnections

A multi-chip package may include first and second semiconductor chips, an insulating layer structure and a plug structure. The first semiconductor chip may include a first bonding pad. The second semiconductor chip may be positioned over the first semiconductor chip. The second semiconductor chip may include a second bonding pad. The insulating layer structure may cover side surfaces and at least portions of upper surfaces of the semiconductor chips. The plug structure may be formed in the insulating layer structure by a plating process. The plug structure may be arranged spaced apart from side surfaces of the semiconductor chips to electrically connect the first bonding pad and the second bonding pad with each other. A third semiconductor chip having a third bonding pad may be positioned over the second semiconductor chip. Thus, a process for forming a micro bump between the plugs need not be performed.

Multi-chip package and method of manufacturing the same

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Semiconductor assembly and semiconductor package including a solder channel

In a method of forming a conductive pattern structure of a semiconductor device, a first insulating interlayer is formed on a substrate. A first wiring is formed to pass through the first insulating interlayer. An etch stop layer and a second insulating interlayer are sequentially formed on the first insulating interlayer. A second wiring is formed to pass through the second insulating interlayer and the etch stop layer. A dummy pattern is formed to pass through the second insulating layer and the etch stop layer at the same time as forming the second wiring. The second wiring is electrically connected to the first wiring. The dummy pattern is electrically isolated from the second wiring.

Semiconductor devices and methods of manufacturing the same

A system on chip (Soc) includes a system bus, a plurality of sub-systems, an image processing logic block, an image memory interface and an image processing memory block. The sub-systems are respectively connected to the system bus. The image processing logic block is connected to the system bus. The image processing logic block performs an image processing. The image processing logic block is included in a first power domain. The image memory interface is connected to the system bus and the image processing logic block. The image processing memory block is connected to the image memory interface. The image processing memory block is used for the image processing. The image memory interface and the image processing memory block are included in a second power domain different from the first power domain.

System on chip including an image processing memory with multiple access

A method of manufacturing a reference sample substrate for analyzing a metal contamination level includes coating an organic silica solution including metal impurities on a semiconductor substrate and forming an oxide layer on the semiconductor substrate by thermally treating the semiconductor substrate having the coated organic silica solution. The metal impurities are substantially uniformly distributed in the oxide layer and the metal impurities are positioned at predetermined portions of the oxide layer.

Methods of manufacturing reference sample substrates for analyzing metal contamination levels

Disclosed herein are a sweetpotato expansin cDNA (IbExpansin), a plant transformation vector carrying the same, and a transgenic plant comprising the vector. The transgenic, prepared using the IbExpansin cDNA, outgrows the wild-type, thereby increasing in size and seed production up to three times. Thus, the gene is useful in the generation of highly productive transgenic plants for improvement in biomass and/or seed production.

Sweetpotato expansin cDNA and high-yield transgenic plants using the same

Growing community of inventors

Seoul, South Korea

Sun-Hee Park