Sun Microsystems, Inc.

Cisco Technology, Inc.

Telefonaktiebolaget Lm Ericsson (publ)

Sun-den Chen

Charles E Narad

Kevin B Normoyle

Satyanarayana Nishtala

William C Van Loo

Zahir Ebrahim

William N Joy

Mark A Ross

Andreas V Bechtolsheim

Robert Yung

Leslie Dean Kohn

Srivathsa Dhruvanarayan

Michael Feng

Edward Ho

Thomas C Yip

Thomas L Lyon

Sanjeev Mahalawat

Christophe Metivier

John McCool

Jeffrey Hu

A method is implemented by a network element to provide scalable hierarchical traffic management (HTM) over a plurality of network layers for a network and eliminate priority leaking caused by quick loopback batch scheduling that analyzes a subset of network layers to shorten processing time and resource requirements when the scalable HTM selects data packets to be forwarded. The method and system function as a low pass filter over the selected data packets to prevent low priority data packets being forwarded where higher priority data packets are available to be forwarded.

Low pass filter for hierarchical pipelined distributed scheduling traffic manager

A SGMII that operates to transfer data between MAC and PHY chips at 2500/1000/100/10 Mbps utilizes a unique frame extending technique in one embodiment where frames having multiples of 2 and 3 data bytes are utilized to change the data transfer rate by multiples of 2.5. In another embodiment different clock signals are utilized.

10/100/1000/2500 Mbps serial media independent interface (SGMII)

An apparatus and method for performing logical operations on information in the communications protocol stack, such as the transport layer (L4) port numbers, characterizing a received packet or frame of data in a data communications device such as a router or switch. The results of the logical operations, along with other packet/frame-identifying data, are used to generate a more efficient lookup key. A content addressable memory (CAM) lookup is used to determine the action indicated by the rules defined by a rule-based routing or switching scheme, such as an access control list (ACL). The results of these logical operations extend the key space and thus provide a finer-grained match between the original, unextended input key and a rule action, thereby pointing to a rule action precisely tailored to packet processing. The rule can thus be applied with fewer CAM entries, providing the versatility improvement and CAM cost reduction necessary to keep up with the ever-increasing rule complexity requirements of advanced data communication and internetworking systems. An embodiment utilizing asymmetrical processing of packets, depending on whether the packet is inbound to the data communications device or outbound from it, is also disclosed. Furthermore, a ternary content-addressable memory (TCAM) implementation is disclosed. Use of a TCAM for ACL or other rule lookups further enhances the efficiency of rule processing by providing a masking capability for each TCAM entry which can be used to provide an additional level of flexibility for rule element checking.

Logical operation unit for packet processing

An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers. When an interrupt request is sent from an interrupter, the system controller determines a target for the request, which may be by a target ID in the request or may be based upon a predetermined method to ensure even distribution of interrupt requests among all or a subset of the interrupt handlers. The system controller determines whether the target interrupt handler's input queue is full, and if not then it passes on the interrupt request and sends a positive acknowledgment to the interrupter. If the queue is full, then a negative acknowledgment is sent, and the interrupter then waits a random period of time and sends the interrupt request again. The target interrupt handler may thus accept multiple interrupt requests and process them in order without negative acknowledgments.

Method and apparatus for interrupt communication in packet-switched

A virtual I/O processor (VIOP) is implemented using a programmed I/O (PIO) unit. The PIO unit is complemented by a VIOP interrupt, a VIOP interrupt handler, and a number of VIOP data structures. Preferably, the PIO unit is further complemented with a set of dedicated I/O global registers, a number of VIOP library read/write routines for various I/O device types, and non-blocking read and write operations. During execution, these elements cooperate with each other to perform multiple sequences of programmed I/Os as if they were being performed by a dedicated I/O processor.

Virtual input/output processor utilizing an interrupt handler

Method and apparatus for interrupt communication in a packet-switched

Deadlock detection and masking systems are incorporated into a bus coupler intercoupling at least two buses, wherein at least one master is coupled to each bus and at least one slave is coupled to at least one of the buses. The bus coupler also includes an arbiter coupled to the buses to determine which master may control each bus. The deadlock detection system detects a potential arbitration deadlock condition between two master devices seeking control of a bus and access to a slave. Once a potential arbitration deadlock is detected, the masking system is activated to prohibit the second master from gaining control of the second bus for a random period of time. The random time delay acts as a mask to provide the first master device an opportunity to reaccess the slave device and avoid the deadlock situation. By providing a random masking period complementary, synchronized arbitration deadlocks are avoided.

Method for preventing deadlock in a multi-bus computer system

A bus-to-bus interface preserves data coherence between masters and slaves operating within a multiple processor computer system. Two buses are connected via the interface. The first bus connects a number of self-identifying masters. The second bus connects a number of master devices and a number of slave devices. The second bus has no mechanism with which devices connected to the second bus may identify themselves. The interface contains a pair of registers for each slave device connected through the second bus. One register stores a busy bit if the corresponding slave is engaged on behalf of a master. The second register stores an identifying code for the master delegating a task to the corresponding slave. When a slave has accepted a task on behalf of a master and commanded the master to relinquish the bus, the busy register will be set and the master identification register will store the identifying code for the delegating master. Thereafter no master will be permitted to access the engaged slave unless the master identification code is that of the delegating master. Moreover, a delegating master will be denied access to the slave by that slave until the slave has completed the task accepted on behalf of the master. By preventing unintended masters from accessing slaves prior to the delegating master, inadvertent data transferred to the wrong master is avoided. Data coherence between master and slave is thereby ensured.

Bus-to-bus interface for preventing data incoherence in a multiple

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San Jose, CA, United States of America

Sun-den Chen