Samsung Electronics Co., Ltd.

Sun-cheol Hong

Yun-Seung Shin

Sang-eun Lee

Young-woo Seo

Dug-dong Kang

Soon-moon Jung

Won-cheol Hong

A method of forming a contact structure in a semiconductor device is provided. In this method, a semiconductor layer, an ohmic metal layer, and a barrier metal layer are formed on the surface of a semiconductor substrate on which a metal contact hole has been formed. A compound material layer having a uniform thickness is formed on the bottom, sidewalls and lower corners of the contact hole by thermally reacting the semiconductor layer with the ohmic metal layer. Accordingly, when the contact hole exposes an impurity layer and portions of an isolation layer adjacent to the impurity layer, the junction leakage current characteristics of the impurity layer and a contact resistance are improved.

Method of forming contact structure in a semiconductor device

Methods of forming integrated circuit memory devices, such as DRAM memory cells, include the steps of simultaneously forming storage electrode and bit line contact regions of first conductivity type in a semiconductor region of second conductivity type. The contact regions preferably receive a double dose of first conductivity type dopants. This double dose compensates for etching damage caused during processing and improves the memory cell's refresh characteristics. The preferred methods of forming DRAM memory cells include the steps of forming an electrically insulating layer on a face of a semiconductor substrate containing a region of second conductivity type therein (e.g., P-type) extending to the face, and then forming a word line (or segment thereof) on the electrically insulating layer, opposite the region of second conductivity type. Contact regions of first conductivity type for a storage electrode and bit line are then formed at the same time at adjacent opposing edges of the word lines by implanting dopants of first conductivity type into the region of second conductivity type using the word line as an implant mask. A storage electrode of a capacitor is then formed on (or coupled to) the storage electrode contact region adjacent a first edge of the word line and a bit line is also preferably formed on (or coupled to) the bit line contact region adjacent a second edge of the word line. The bit line contact region and storage electrode contact region preferably receive a double dose of first conductivity type dopants by performing a first ion implant step, forming sidewall spacers on the first and second edges of the word line and then performing a second ion implant step using the sidewall spacers as an implant mask.

Methods of forming integrated circuit memory devices having improved bit

A method for forming an electrode for an integrated circuit device includes the steps of forming a first insulating layer on a semiconductor substrate and forming a conductive mesa on the first insulating layer. The insulating layer has a contact hole therein exposing a portion of the substrate, and the conductive mesa covers and extends into the contact hole so that the conductive mesa is electrically connected to the substrate. A second insulating layer is formed on the first insulating layer wherein the second insulating layer surrounds the conductive mesa and wherein the second insulating layer has a second thickness greater than the first thickness. Accordingly, sidewalls of the second insulating layer are exposed adjacent the conductive mesa. Spacers are formed on the conductive mesa along the sidewalls of the second insulating layer, and the conductive mesa is etched using the second insulating layer and the spacers as an etching mask.

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Incheon, South Korea

Sun-cheol Hong