Silicon Graphics, Incorporated

Intel Corporation

Mips Computer Systems, Inc.

Sun C Chan

Raymond W Lo

Frederick Chow

Shin-Ming Liu

Mark Streich

Peng Tu

Robert Kennedy

James C Dehnert

Yang Liu

Guei-Yuan Lueh

Xin Zhou

Dawei Wang

Dror E Maydan

Shaojun Wei

Leibo Liu

Peter Dahl

Shouyi Yin

Shanshan Zheng

Sai Luo

Jiqiang Song

Jesse Z Fang

Wilson Ho

Dz-ching (Roy) Ju

Chunxiao Lin

Eugene Tang

Randolph Wang

Ross A Towle

Zhaoqing Zhang

Li Shang

Suneel Jain

Paul Peng

Jack C Carter

W Wilson Ho

Guangrong Gao

David L Stephenson

Chandrasekhar Murthy

Sin S Lew

A system of extending functionalities of a host device using a smart flash storage device comprises the host device having a host interface and configured to perform a specific function to generate a first set of data. The host device is coupled with a flash storage device. The flash storage device is configured to conform to a flash memory interface. A set of data generated by the host device is to be stored in flash memory storage of the flash storage device. A processor of the flash storage device is configured to run one or more user applications to process the set of data. The processor is to operate using power supplied by the host device.

Extending the capabilities of existing devices without making modifications to the existing devices

According to some embodiments, a communication modulemay be configured to transmit data packet traffic and a management modulemay be configured to shape the data packet traffic transmitted by the communication module. The management modulemay shape the data packet traffic by buffering data packets routed at different times to the communication modulebased on at least one power management factor.

Shaping data packet traffic

A method for an allocation of stacked registers for Intel's Itanium&#xae; processor includes a three step process. Step I determines an intra-procedural stacked register usage by a program having a plurality of procedures. In step II, the disclosed method performs an inter-procedural analysis to assign quota of stacked register usage to every procedure. In step III, each procedure is allocated stacked register usage based on the quota assignments of step II.

Inter-procedural allocation of stacked registers for a processor

A method and computer program product, within an optimizing compiler, for precise feedback data generation and updating. The method and computer program uses instrumentation and annotation of frequency values to allow feedback data to stay current during the multiple optimizations that the program code undergoes during compilation. Global propagation of known precise feedback values are used to replace approximate and unavailable values, and global verification of feedback data after optimization to detect discrepancies is employed. The method and computer program also provides improved instrumentation to anticipate cloning when code is cloned during ceratin compiler optimizations and handles inlined procedures. The result is compiled executables with improved SPECint benchmarks.

Method and computer program product for precise feedback data generation and updating for compile-time optimizations

A method, system, and computer product uses a hashed static single assignment (SSA) form as a program representation and a medium for performing global scalar optimization. A compiler, after expressing the computer program in SSA form, can perform one or more static single assignment (SSA)-based, SSA-preserving global scalar optimization procedures on the SSA representation. Such a procedure modifies, (i.e., optimizes) the SSA representation of the program while preserving the utility of its embedded use-deprogram information for purposes of subsequent SSA-based, SSA-preserving global scalar optimizations. This saves the overhead expense of having to explicitly regenerate use-def program information for successive SSA-based, SSA-preserving global scalar optimizations.

Method, system, and computer program product for using static single assignment form as a program representation and a medium for performing global scalar optimization

A system and method for an optimizer of a compilation suite for representing aliases and indirect memory operations in static single assignment (SSA) during compilation of a program having one or more basic blocks of source code. The optimizer converts all scalar variables of said program to SSA form, wherein said SSA form includes a plurality of variable versions, zero or more occurrences of a .chi. function, zero or more occurences of a .phi. function, and zero or more occurrences of a .mu. function. The .chi. function, .phi. function, and .mu. function are inserted for the variable versions. The optimizer also determines whether a variable version can be renamed to a zero version, and upon such a determination, the optimizer renames the variable version to a zero version. The optimizer further converts all indirect variables of a program to SSA form, wherein the SSA form includes a plurality of virtual variable versions such that a virtual variable is assigned to an indirect variable, zero or more occurrences of a .chi. function, zero or more occurences of a .phi. function, and zero or more occurrences of a .mu. function. The .chi. function, .phi. function, and .mu. function are inserted for the virtual variables. The optimizer hashes a unique value number and creates a corresponding hash table entry for each variable version and each virtual variable remaining after renaming all zero versions. The optimizer also applies global value numbering to each basic block of the program.

System and method to efficiently represent aliases and indirect memory

A method, system, and computer program product for performing register promotion, that optimizes placement of load and store operations of a computer program within a compiler. Based on the observation that the circumstances for promoting a memory location's value to register coincide with situations where the program exhibits partial redundancy between accesses to the memory location, the system is an approach to register promotion that models the optimization as two separate problems: (1) the partial redundancy elimination (PRE) of loads and (2) the PRE of stores. Both of these problems are solved through a sparse approach to PRE. The static single assignment PRE (SSAPRE) method for eliminating partial redundancy using a sparse SSA representation representations the foundation in eliminating redundancy among memory accesses, enabling the achievement of both computational and live range optimality in register promotion results. A static single use (SSU) representation is defined allowing the dual of the SSAPRE algorithm, called SSUPRE, to perform the partial redundancy elimination of stores. SSUPRE is performed after the PRE of loads, taking advantage of the loads' having been converted into pseudo-register references so that there are fewer barriers to the movement of stores. Consequently, the compiler produces more efficient, register-promoted executable program code from the SSA representation.

Method, system, and computer program product for performing register

Partial redundancy elimination of a computer program is described that operates using a static single assignment (SSA) representation of a computer program. The SSA representation of the computer program is processed to eliminate partially redundant expressions in the computer program. This processing involves inserting .PHI. functions for expressions where different values of the expressions reach common points in the computer program. A result of each of the .PHI. functions is stored in a hypothetical variable h. The processing also involves a renaming step where SSA versions are assigned to hypothetical variables h in the computer program, a down safety step of determining whether each .PHI. function in the computer program is down safe, and a will be available step of determining whether each expression in the computer program will be available at each .PHI. function following eventual insertion of code into the computer program for purposes of partial redundancy elimination. The processing also includes a finalize step of transforming the SSA representation of the computer program having hypothetical variables h to a SSA graph that includes some insertion information reflecting eventual insertions of code into the computer program for purposes of partial redundancy elimination, and a code motion step of updating the SSA graph based on the insertion information to introduce real temporary variables t for the hypothetical variables h.

System, method, and computer program product for partial redundancy

A system and method of eliminating some of the indirect addressing associated with Position Independent Code (PIC). The invention applies cross-module optimization to dynamic linking of shared libraries. A definition table is built that defines where each symbol within an application program and associated shared library is defined. Also stored in the definitions table is an associated attribute. The definition table is utilized to eliminate indirect addressing wherever possible. As a result, overall system performance is increased.

Cross-module optimization for dynamically-shared programs and libraries

In a computer system having a cache memory and a main memory for storing data, a method for laying out blocks of data to minimize a number of memory transfers between the cache memory and the main memory. Memory layout normally occurs at link time, after all the source files have been compiled. The code is compiled with the assumption that the memory blocks can be optimally placed. The linker then determines whether there has been any memory violations. Memory violations are marked. All marked memory locations are then placed in a layout that satisfies adjacency requirements.

Compiler having automatic common blocks of memory splitting

A system and method for optimizing a source code representation comprising a plurality of basic blocks are described. The optimized source code representation is to be executed in a target machine. The system operates by selecting from the source code representation a basic block pair comprising a source basic block and one or more target basic blocks. An instruction in the source basic block is identified that can be moved from the source basic block to the target basic block(s) while preserving program semantics. Either the instruction or a representation of the instruction is moved from the source basic block to the target basic block(s) as a function of resource utilization of the target machine that would result from this movement.

System and method for optimizing a source code representation as a

A system and method of generating object code from an intermediate representation of source code is described. The intermediate representation includes a plurality of basic blocks each being represented by a plurality dam dependency graphs, wherein each data dependency graph comprises a plurality of nodes each corresponding to an instruction from the target computer instruction set. The present invention operates by selecting a source basic block (that is one of the basic blocks of the intermediate representation) and a target basic block (that is another of the basic blocks of the intermediate representation), and by identifying a maximal set of instructions contained in the source basic block that are movable from the source basic block to the target basic block without violating any data dependency relationships of the data dependency graphs. An overall cost model of aggregately moving instructions of the maximal set from the source basic block to the target basic block is generated. This cost model specifies an executable cost of moving each of the instructions of the maximal set from the source basic block to the target basic block. Then, the present invention aggregately moves one or more instructions of the maximal set from the source basic block to the target basic block according to the cost model to form the object code.

System and method of generating object code using aggregate instruction

A procedure which is a particular type of software pipelining is provided which increases the efficiency with which code is executed by reducing or eliminating stalls such as by filling delay slots. The process includes moving instructions in a loop from one loop iteration to another. The moving of instructions provides the scheduler with additional independent instructions in a given basic block so the scheduler has greater freedom to move instructions into unfilled delay slots. The procedure includes changing the entry point into the loop, thus effectively moving an instruction from near the top of the loop to near the bottom of the loop, while changing the iteration number of the moved instruction.

Circular scheduling method and apparatus for executing computer programs

Growing community of inventors

Fremont, CA, United States of America

Sun C Chan