Samsung Electronics Co., Ltd.

Sun-Ae Seo

Do-Young Kim

Young-Jin Cho

In-kyeong Yoo

Myoung-jae Lee

Wan-jun Park

Won-Joo Kim

Young-Soo Park

Young-min Choi

Jang-yeon Kwon

June-key Lee

In-gyu Baek

Seung-eon Ahn

Jang-Eun Lee

David Seo

Sung-Chul Lee

Soo-hwan Jeong

Sung-do Moon

Yo-sep Min

Soo-doo Chae

In-Sook Kim

Byung-Chang Cha

Dae-Hyun Cho

Sang-Hun Jeon

In-Kyeong Yoo

Dong-seok Suh

Sang-min Shin

Dong-Chul Kim

Hyeong-jun Kim

Young-Kwan Cha

Choong-rae Cho

Sang-Jin Park

Jong-Tae Kim

Eun-Kyung Yim

Dong-Jun Shin

Yoon-dong Park

Ung-Hwan Pi

Hee-Sub Shin

In-Gyu Baek

Hyun-jo Kim

In-sook Kim

In-jae Song

Seung-Eon Ahn

Myoung-Jae Lee

Ji-Young Bae

Byoung-Ho Park

Yong-Soo Joung

David c/o Samsung Advanced Institute Seo

Young-Kwan c/o Samsung Advanced Institute Cha

A method of managing a memory in an electronic device is provided that includes calculating an indication of remaining life of a memory component that is used as a swap space by the electronic device; and adjusting the use of the memory component as a swap space based on the indication of remaining life, wherein the adjusting includes one of: (i) reducing a rate at which data is swapped in and out of the memory component, and (ii) discontinuing the use of the memory component as a swap space.

Controlling swap rate based on the remaining life of a memory

An apparatus and method for optimizing an application to be executed in an execution environment of a client are provided. For example, on-demand optimizing of the performance of applications may be performed such that the applications are suitable for execution environments of various types of Consumer Electronic (CE) equipment, in order to distribute high performance applications.

Apparatus and method for on-demand optimization of applications

Provided are an apparatus and method for executing an application. Using the apparatus and method, an application is executed in a terminal directly, or by receiving a computing service from a remote server. After an execution time and/or power consumption of when the application is executed in the terminal directly, and an execution time and/or power consumption when the computing service is received from the remote server are estimated, one of the application execution methods of the two cases may be selected according to the estimated values. The estimated values may be determined based on a state of the terminal, the quality of service (QoS) state of the remote server, and a characteristic of the application.

Apparatus and method for executing an application

A method of analyzing single thread access by a variable of a multi-threaded program is provided. The method includes computing a thread identifier of a thread to be executed in a node of the multi-thread program; computing multiple threads configured to concurrently execute the node; and computing thread accessibility by deducing one or more variables that are executed in a single thread of the program from one or more pairs of the computed threads that concurrently execute the node.

Method of analyzing single thread access of variable in multi-threaded program

A nonvolatile memory device including one transistor and one resistant material and a method of manufacturing the nonvolatile memory device are provided. The nonvolatile memory device includes a substrate, a transistor formed on the substrate, and a data storage unit connected to a drain of the transistor. The data storage unit includes a data storage material layer having different resistance characteristics in different voltage ranges.

Nonvolatile memory device comprising one switching device and one resistant material and method of manufacturing the same

A method of manufacturing a nanochannel-array and a method of fabricating a nanodot using the nanochannel-array are provided. The nanochannel-array manufacturing method includes: performing first anodizing to form a first alumina layer having a channel array formed by a plurality of cavities on an aluminum substrate; etching the first alumina layer to a predetermined depth and forming a plurality of concave portions on the aluminum substrate, wherein each concave portion corresponds to the bottom of each channel of the first alumina layer; and performing second anodizing to form a second alumina layer having an array of a plurality of channels corresponding to the plurality of concave portions on the aluminum substrate. The array manufacturing method makes it possible to obtain finely ordered cavities and form nanoscale dots using the cavities.

Method of manufacturing self-ordered nanochannel-array and method of manufacturing nanodot using the nanochannel-array

A multi-bit memory cell stores information corresponding to a high resistive state and multiple other resistive states lower than the high resistive state. A resistance of a memory element within the multi-bit memory cell switches from the high resistive state to one of the other multiple resistive states by applying a corresponding current to the memory element.

Multi-state resistive memory element, multi-bit resistive memory cell, operating method thereof, and data processing system using the memory element

In a thin film semiconductor device realized on a flexible substrate, an electronic device using the same, and a manufacturing method thereof, the thin film semiconductor device and an electronic device include a flexible substrate, a semiconductor chip, which is formed on the flexible substrate, and a protective cap, which seals the semiconductor chip. Durability of the thin film semiconductor device against stress due to bending of the substrate is improved by using the protective cap.

Method for manufacturing electronic device using thin film transistor with protective cap over flexible substrate

A memory device using a multi-layer with a graded resistance change is provided. The memory device includes: a lower electrode; a data storage layer being located on the lower electrode and having the graded resistance change; and an upper electrode being located on the data storage layer.

Memory device using multi-layer with a graded resistance change

A memory device and a method of fabricating the same are provided. The method includes forming a gate stack on a semiconductor substrate and partially exposing upper end portions of the semiconductor substrate by etching the gate stack to form a gate stack structure, and implanting a dopant into the exposed portions of the semiconductor substrate to form source and drain regions, wherein the gate stack structure is etched such that its width increases from top to bottom. Accordingly, it is possible to manufacture a memory device with high integration, using a simplified manufacture process.

Memory device and method of manufacturing the same

Disclosed are a muli-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the muli-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of channels disposed perpendicularly to the upper surface of the semiconductor substrate; a plurality of storage nodes disposed on opposite sides of the channels perpendicularly the upper surface of the semiconductor substrate; a control gate surrounding upper portions of the channels and the storage nodes, and side surfaces of the storage nodes; and an insulating film formed between the channels and the storage nodes, between the channels and the control gate, and between the storage nodes and the control gate.

Multi-bit non-volatile memory device, method of operating the same, and method of manufacturing the multi-bit non-volatile memory device

Thin film transistor with protective cap over flexible substrate, electronic device using the same, and manufacturing method thereof

A memory device having one transistor and one resistant element as a storing means and a method for driving the memory device, includes an NPN-type transistor formed on a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate to cover the transistor in which a contact hole exposing a source region of the transistor is formed, a resistant material in which a bit data '0' or '1' is written connected to the source region of the transistor by a conductive plug or an insulating film, and a conductive plate contacting the resistant material. The memory device exhibits improved degree of integration, reduced current consumption by lengthening a refresh period thereof, and enjoys simplified manufacturing process due to a simple memory cell structure.

Memory device having a transistor and one resistant element as a storing means and method for driving the memory device

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Seoul, South Korea

Sun-Ae Seo