International Business Machines Corporation

The Penn State Research Foundation

Sumitha George

James Douglas Warnock

Ayan Datta

Charudhattan Nagarajan

Vijay K Ankenapalli

Suman Datta

John Sampson

Vijaykrishnan Narayanan

Xueqing Li

Sumeet Kumar Gupta

Kaisheng Ma

A computer-implemented method includes receiving a text description of a logic circuit design, reading a plurality of circuit priority indicator values, synthesizing a logic circuit design based, at least in part, on those circuit priority indicator values, and fabricating logic circuits using the synthesized logic circuit design. A corresponding computer program product and computer system are also disclosed herein.

Priority based circuit synthesis

Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I&#x2212;Vhysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two Istates at V=0.

Nonvolatile digital computing with ferroelectric FET

Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I-Vhysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two Istates at V=0.

A computer-implemented method includes receiving, with one or more processors, a text-based description of a logic circuit comprising a plurality of logic sub-circuits, determining within the text-based description, with one or more processors, a set of circuit priority indicators for a corresponding set of the logic sub-circuits, and synthesizing, with one or more processors, the logic circuit according to the set of circuit priority indicators to provide a synthesized circuit description. A corresponding computer program product and computer system are also disclosed herein.

Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.

Programmable delay circuit including hybrid fin field effect transistors (finFETs)

Various embodiments include: determining boundary vertices for an ECO within a placed netlist based on: a first weight assigned to a gate array distribution; and a second weight assigned to routing congestion, the boundary vertices defining a polygon; implementing the ECO at gate level; estimating slack value for determined boundary vertices; assigning vertex weights to boundary vertices based on the estimated slack values for boundary vertices; calculating a weighted centroid location for the polygon, based on the vertex weights; locating spare latches in the placed netlist; determining a clock domain and a clock gating domain for each located spare latch; assigning a cost function to each located spare latch having a same clock domain and a same clock gating domain as the ECO; ranking each respective cost function for each located spare latch; and selecting the desired spare latch based on the ranking of the each located spare latch.

Growing community of inventors

State College, PA, United States of America

Sumitha George