Fujitsu Corporation

Sumitaka Hibino

Masayuki Takeshige

Kenji Yamada

Kazuya Taniguchi

Kunihiro Ohara

Yukisato Miyazaki

Hiroshi Naritomi

Hayato Isobe

Teruyoshi Kondo

Method and system for shortening the time needed to test a semiconductor device having a plurality of memory circuits. The semiconductor device includes an address decoder for selecting a plurality of memory circuits and causing the memory circuits to perform a read/write operation. A comparator receives plural pieces of read data read from the plurality of memory circuits and compares the plural pieces of read data with one another. A processing unit compares one of the plural pieces of read data with write data. Using the comparison results of the comparator and the processing unit shorten the time needed to test the plurality of memory circuits.

Test method and test system for semiconductor device

A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores the lower order bits in a lower order bit storage section and the higher order bits in a higher order bit storage section. The lower order bits and the corresponding higher order bits are read from the memory in the same cycle when generating the instruction code.

Method and apparatus for compactly storing instruction codes

Growing community of inventors

Kasugai, Japan

Sumitaka Hibino