Cadence Design Systems, Inc.

Sumit Roy

Krishna Prasad Belkhale

Devadas Varma

Qi Wang

The present invention provides a method and mechanism for optimizing the power consumption of a micro-electronic circuit. According to an embodiment, when optimizing the power consumption of a micro-electronic circuit, one or more candidates for applying one or more optimization techniques may be identified. Then, the one or more candidates may be marked with the one or more optimization techniques within the micro-electronic circuit without altering the data and/or control paths of the circuit. Then, after timing and logic optimization, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique saves power and/or satisfies the timing requirement of the circuit. Further, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique is reducible, and if so, then the technique may be reduced to determine whether such reduction improves the circuit's timing.

Method and mechanism for RTL power optimization

Provided are a method, article of manufacture, and apparatus for matching candidate clusters to cells in a technology library. An automated design system comprises a computer configured to use second order signatures in generating candidate permutations of each permutation group in a canonical form of the candidate function. The system selects first and second symmetric subgroups, determines a second order signature for the candidate function and the first and second symmetric subgroups, and compares the second order signature to a corresponding second order signature for a library cell function. If the signatures match, the permutation is continued with the first and second symmetric subgroups being included in an intermediate permutation. If not, the system produces no more intermediate permutations beginning with the first and second symmetric subgroups. Further symmetric subgroups are added to the intermediate permutation. For each new symmetric subgroup, the system produces pairings of that symmetric subgroup with each of the symmetric subgroups in the intermediate permutation, and compares the second order signatures of the pairings to corresponding second order signatures in the library function. If at any time any of the second order signatures do not match their corresponding library function signatures, the system produces no more intermediate permutations beginning with the current sequence of the intermediate permutation, and instead removes the new symmetric subgroup and attempts to continue building the previous intermediate permutation. When all symmetric subgroups in the permutation group have been added to the intermediate permutation, the intermediate permutation becomes a candidate permutation.

Cluster matching for circuit implementation

Provided are a method, article of manufacture, and apparatus for identifying candidate clusters for matching to cells in a technology library. An automated design system comprises a computer configured to extract a portion of a circuit, levelize it, select a first node, identify the realizable clusters at the inputs of the first node, and combine the first node with realizable clusters at the inputs to produce candidate clusters. A dummy cluster is used at each input to represent using the input as a fanin. The system takes the cross product of the sets, and the first node is merged with each element of the cross product to produce a set of candidate clusters. The candidate clusters are then checked for realizability by comparing them to cells in the technology library, which includes dummy cells to facilitate mapping to large cells in the technology library. A set of realizable clusters is produced for the first node. The system applies the same process to successive nodes in the levelized circuit, including in the intermediate set the sets of realizable clusters for preceding nodes.

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Evanston, IL, United States of America

Sumit Roy