Calypto Design Systems, Inc.

Mentor Graphics Corporation

Xilinx, Inc.

Sumit Roy

Anmol Mathur

Venky Ramachandran

Nikhil Tripathi

Malay Haldar

Mohit Kumar

Abhishek Roy

Sonal Santan

Stephen P Rozum

Sudipto Chakraborty

Yenpang Lin

Yau-Tsun Steven Li

Gagan Hasteer

Aiguo Xie

Fei Rui

A system, method and computer program product are provided for conditionally eliminating a memory read request. In use, a memory read request is identified. Additionally, it is determined whether the memory read request is an unnecessary memory read request. Further, the memory read request is conditionally eliminated, based on the determination.

System, method, and computer program product for conditionally eliminating a memory read request

Hardware acceleration for a kernel can include selecting, using a processor, a kernel, determining, using the processor, a clock frequency for the selected kernel, and programming, using the processor, a clock circuit to generate a clock signal having a clock frequency compatible with the clock frequency of the selected kernel. Using the processor, the selected kernel can be implemented as a kernel circuit within a region of programmable circuitry. The kernel circuit can be clocked using the clock signal from the clock circuit having the compatible clock frequency.

Adaptive compilation and execution for hardware acceleration

An integrated circuit design system, method, and computer program product are provided that takes into account signal stability. In use, at least one condition is identified where an output of a logic element before receipt of a clock signal is the same as the output of the logic element after receipt of the clock signal. To this end, such logic element may be disabled based on the identified condition for power savings or other purposes.

Integrated circuit design system, method, and computer program product that takes into account the stability of various design signals

An integrated circuit design system, method, and computer program product are provided that takes into account observability based clock gating conditions. In use, at least one condition is identified where an output of a first logic element is not a function of a first input of the first logic element, due to a second input of the first logic element. To this end, at least one second logic element may be disabled based on the identified condition for power savings or other purposes.

Integrated circuit design system, method, and computer program product that takes into account observability based clock gating conditions

A system, method and computer program product are provided for simultaneous cell identification/technology mapping. In use, a plurality of data operators is received. Further, at least two cells are identified for each data operator, simultaneously with technology mapping. By this design, at least one of the cells may thus be selected for design optimization purposes.

System and computer program product for simultaneous cell identification/technology mapping

A method and a system for inplace symbolic simulation of circuits. This method is applicable to both single clock and multiple clock domain designs. The method performs inplace symbolic simulation by appending slots to the various objects of the circuit. The slot associated with an object is a function of time, and it represents the functionality of the element at a given time. The method comprises the steps of determining a phase-list, determining ticks associated with each object of the circuit. Based on these ticks, slots are generated. Further, relations between the slots of the various objects of the circuit are captured.

Method and system for inplace symbolic simulation over multiple cycles of a multi-clock domain design

Growing community of inventors

San Jose, CA, United States of America

Sumit Roy