Xilinx, Inc.

Sumit Nagpal

Siddharth Rele

Avdhesh Palliwal

Srinivasan Dasasathyan

Padmini Gopalakrishnan

Prashanth Kumar

David A Knol

David Robinson

Frederic Revenu

Gangadhar Budde

Shreegopal S Agrawal

Brendan Matthew O'Higgins

Meghraj Kalase

Arun Kumar Patil

Abid Karumannil

Vishal K Jain

John Blaine

Veeresh Pratap Singh

Satish Bachina

Vikas N Vedamurthy

Sreevidya Maguluri

Yogesh Gathoo

Gregory A Brown

Shail Bains

Vishal Tripathy

Gaurav Dutt Sharma

Scheduling work of a machine learning application includes instantiating kernel objects by a computer processor in response to input of kernel definitions. Each kernel object is of a kernel type indicating a compute circuit. The computer processor generates a graph in a memory. Each node represents a task and specifies an assignment of the task to one or more of the kernel objects, and each edge represents a data dependency. Task queues are created in the memory and assigned to queue tasks represented by the nodes. Kernel objects are assigned to the task queues, and the tasks are enqueued by threads executing the kernel objects, based on assignments of the kernel objects to the task queues and assignments of the tasks to the kernel objects. Tasks are dequeued by the threads, and the compute circuits are activated to initiate processing of the dequeued tasks.

Scheduling processing of machine learning tasks on heterogeneous compute circuits

Strategies are stored in a memory arrangement, and each strategy includes a set of parameter settings for a design tool. The design tool identifies a set of features of an input circuit design and applies classification models to the input circuit design. Each classification model indicates one the strategies, and application of each classification model indicates a likelihood that use of the strategy would improve a metric of the input circuit design based on the set of features of the input circuit design. One strategy of the plurality of strategies is selected based on the likelihood that use of the one strategy would improve the metric of the input circuit design, and the design tool is configured with the set of parameter settings of the one strategy. The design tool then processes the input circuit design into implementation data that is suitable for making an integrated circuit (IC).

Automated analysis and optimization of circuit designs

Disclosed approaches for guiding actions in processing a circuit design include a design tool identifying first violations of design checks and determining severity levels of the first violations. The design tool determines for each violation, suggested actions associated with the violation and presents on a display, first data indicative of the suggested actions in order of the severity levels of the first violations. The first data include selectable objects, and each selectable object has an associated executable procedure. The design tool can execute the procedure associated with one of the selectable objects in response to selection and modify the circuit design in response to execution of the procedure.

System and method for an electronic design tool providing automated guidance and interface for circuit design processing

Core processing and parameterization may include detecting, using a processor, a super parameter within a core, and, responsive to the detecting, automatically creating, using the processor, a data structure within a memory element having a hierarchy and having a parameter of the core. The data structure may be set as a value of the super parameter of the core.

Dynamic discovery and presentation of core parameters

Implementing a circuit design may include, responsive to a user input selecting a design, executing an implementation script of the design using the processor. Executing the implementation script may generate instructions for generating a circuit design from the design. Responsive to the instructions and using the processor, cores of the design may be automatically instantiated and connected.

Delivering circuit designs for programmable integrated circuits

A method of processing a circuit design in a circuit design tool includes: identifying selection of a parameterized core to be instantiated in a description of the circuit design managed by the circuit design tool and configured for implementation in target hardware; processing a configuration file for the parameterized core to select a set of parameter values from a plurality of sets of parameter values dynamically based at least in part on the target hardware; creating an instance of the parameterized core in the circuit design having the selected set of parameter values; and implementing the circuit design for the target hardware.

Circuit design with predefined configuration of parameterized cores

An exemplary method of implementing a circuit design for a programmable integrated circuit (IC) includes, on at least one programmed processor, performing operations including: generating a description of circuit components of the circuit design including first portion of a circuit module that is independent of assignment of resources of the programmable IC; assigning a plurality of the resources of the programmable IC to a plurality of the circuit components including determining at least one resource assignment for the circuit module; and generating a physical implementation of the circuit components for implementation in the programmable IC, including generating a second portion of the circuit module that is dependent on the at least one resource assignment, and combining the second portion of the circuit module with the first portion of the circuit module.

Circuit module generation for programmable integrated circuits

A user interface for a computer-aided design tool includes a display. The display includes a visualization of a processor system of a system-on-a-chip (SOC). The visualization includes a plurality of blocks and each block represents a component of the processor system. Each block visually indicates a configuration status of the component represented by the block.

Computer aided design tool and user interface for configuration of a programmable system-on-a-chip

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Hyderabad Telangana, India

Sumit Nagpal