Microchip Technology Inc.

Other

Microchip Technologies, Inc.

Sumit K Mitra

Joseph W Triece

Rodney J Drake

Randy L Yach

Darrel Johansen

Edward Brian Boles

Ajay J Padgaonkar

Russ Cooper

Bryan Kris

Igor Wojewoda

Stephen Bowling

Pieter Schieke

Brian E Boles

Ray L Allen

Joshua M Conner

James H Grosbach

Greg Italiano

Martin Burghardt

Harry Hu

Hassan Harb

Kurt Rosenhagen

Steven Marsh

Chao-Wu Chen

Richard Fischer

James Grosbach

Rodney Jay Drake

Darrel Ray Johansen

Johansen Darrel

A successive approximation register analog-to-digital converter (SAR ADC) having a sample, hold and convert amplifier circuit may be configured for either a single channel SAR ADC or a multiple channel SAR ADC. Switches or metal connection options, e.g., bit configurable or metal mask configurable, respectively, may be used to configure a common capacitor area, a portion of which may be used as a reconfigurable charge-redistribution digital-to-analog converter (CDAC) of the SAR ADC as either a single channel sample, hold and convert 12-bit capacitor configuration or a four channel sample, hold and convert 10-bit capacitor configuration. All other parts of the SAR ADC circuitry may be substantially the same for either configuration, e.g., the resistive digital-to-analog converter (RDAC), successive approximation register (SAR), ADC controller, sample, hold and convert switches, comparator, etc, may be substantially the same for either the single or multiple channel SAR ADC configurations.

Analog-to-digital converter with interchangeable resolution and sample and hold amplifier channels

A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performances and decreasing program memory usage.

Microcontroller instruction set

A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used to some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus, increasing performance and decreasing program memory usage.

A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performance and decreasing program memory usage.

A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.

Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor

The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between one or more semiconductor integrated circuit dice, including an IC package and the circuitry of a system wherein the integrated circuit dice is a digital signal controller. Even more particularly, the present invention relates to a 18, 28, 40, 44, 64 or 80 pin functional pathway configuration for the interface between the digital signal controller and the system in which it is embedded.

Functional pathway configuration at a system/IC interface

A processor architecture scheme which allows for encoding multiple addressing modes and which has multiple sources for generating a bank address value. The processor architecture scheme has a Central Processing Unit (CPU) for executing an instruction set. A data memory is coupled to the CPU. The data memory is used for storing and transferring data to and from the CPU. The data memory is divided into a plurality of banks wherein one of the plurality of banks is a dedicated bank for general and special purpose registers. A selection circuit is coupled to the data memory. The selection circuit is used for selecting one of the multiple sources for generating the bank address value. A bank select register is coupled to the selection circuit. The bank select register is used for supplying a bank address value for an instruction to be executed in a direct short addressing mode. An instruction register is coupled to the selection circuit for supplying a bank address values for an instruction to be executed in a direct long addressing mode and for supplying a register address within a bank for the instruction to be executed in a direct short addressing mode.

Processor architecture scheme having multiple bank address override

A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

Processor architecture scheme and instruction set for maximizing

A microcontroller device is fabricated in a semiconductor integrated circuit chip for controlling an external system with which the microcontroller device is to be installed in circuit. The device includes a CPU, a program memory, a data memory, and peripherals for use in controlling the external system. An on-chip peripheral timing module establishes the timing of and degree of control exercised over the external system by a generating a repetitive event configured as a pulse waveform. The timing module is adapted for selectively setting the period of the pulse waveform to designate the frequency of occurrence of the repetitive event for the timing of control and to provoke a corresponding periodic interrupt of the CPU. The width of the pulse in each period of the pulse waveform is selectively modulated to set the degree of control. The timing module selectively varies the frequency of periodic interrupts of the CPU without affecting the period of the pulse waveform. In one embodiment, the selective variation of frequency of the periodic interrupts is performed by a divider circuit.

Microcontroller with programmable postscaler for pulse width modulation

A microcontroller chip with a central processing unit (CPU) is adapted to control an external system with which the device is to be installed in circuit. The microcontroller chip includes an on-chip peripheral universal timing function module with a register for storing a value selected to signify a distinctive event in a waveform. A timer generates a series of values as a function of time as a measure of the value selected to signify the distinctive event. The register and the timer are coupled to a pin of the microcontroller chip on which said waveform is to be applied. Equality between the values in the timer and the register signify the distinctive event as one of a capture and a compare of an event in the waveform, to generate an interrupt to the CPU. The register is selectively split into separate master and slave registers for automatic synchronization of the transfer of a value entered into the master register to the slave register with a repetitive boundary of the waveform, to provide selective pulse width modulation of the waveform.

Microcontroller with multiple timing functions available in a single

A microcontroller fabricated on a semiconductor chip is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. A clock generates timing signals to control the timing of the microcontroller execution and operation. An on-chip program memory has space avilable for storing a program to be executed by the microcontroller in sequential steps in successive address locations of the program memory. An instruction stored in unerasable memory on the chip initiates self-programming of the program memory with the program to be executed by the microcontroller by enabling a pointer timed by the clock to alternately read addresses containing steps of the program to be executed from off-chip memories and to write same into successive addresses of the on-chip program memory by incrementing the latter addresses with each step to be written therein.

Self-progamming of on-chip program memory for microcontroller at clock

A microcontroller and associated EPROM program memory are fabricated in a single semiconductor chip. The microcontroller device is adapted to be programmed using digital command words or other bit patterns applied as inputs after installation of the device in circuit with a system to be controlled by the device, and to have its programming pins isolated from the system to avoid effects on system operation while the programming is taking place. The in-circuit programming uses considerably less than the total number of input/output (I/O) pins of the device, which in total are fewer than the number of bits in a command word. This is achieved with a serial/parallel programming interface between the pins and the program memory, and by applying the data in serial fashion to the interface where it is latched and loaded in parallel in the memory. Input data to the device may alternatively be entered in parallel to the interface in bytes of width less than the total number of I/O pins of the device.

System having input output pins shifting between programming mode and

A microcontroller is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. The microcontroller includes a power supply for supplying power to the overall device within a predetermined range suitable for its operation, and a clock for supplying a clock frequency to the microcontroller with a stability suitable for precise timing and counting within the device. The microcontroller is selectively reset to prevent it from executing programs and instructions for purposes of generating the control signals, and is maintained in the reset condition despite initiation of a removal from the reset condition, until the power supplied by the power supply is in a predetermined range and the clock frequency supplied by the clock is stable. In this way, no execution by the microcontroller is permitted until device stability is achieved, to prevent errors in execution. In the disclosed embodiment, the reset condition is maintained by a power-up timer and an oscillator start-up timer, each timer having a programmable timeout interval to end the reset condition only when the timeout intervals of both timers have expired.

Microcontroller power-up delay

A semiconductor microcontroller includes the capability to perform analog to digital conversions of an analog signal representative of a variable parameter indicative of the need to exercise a control function. While the analog to digital conversions are being performed, the microcontroller processor can be powered down to eliminate noise arising from switching activities of the processor as a source of inaccuracy in the conversion process. At the end of the conversion, the analog to digital converter can either shut itself down or wake up the processor. The powering down is achieved by simply disabling the clock input to the microcontroller so that the processor is still activated but incapable of undergoing switching functions.

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Tempe, AZ, United States of America

Sumit K Mitra