International Business Machines Corporation

Sumit Dasgupta

Thomas W Williams

Matthew C Graf

Robert A Rasmussen

Prabhakar Goel

James H Kukula

Roger E Peo

John M Hancock

A multiprocessing system has a plurality of processors each having a unique interrupt. An executive processor issues interrupt requests over a global bus having a plurality of interrupt lines. A plurality of bus interface systems are each connected to a different interrupt line in the global bus and to a cell bus. A master cell processor and a plurality of slave cell processors are connected to different interrupt lines in the cell bus. All interrupt requests to a cell go first to the master cell processor and then to a slave processor as appropriate.

Interrupt mechanism for multiprocessing system having a plurality of

Disclosed is a design discipline, or approach, in the form of circuitry and a test method, or methodology which obviates the problems of the prior art and allows testing of each individual chip and interchip connections of a plurality of interconnected chips contained on or within a high density packaging structure. This testing is accomplished without the need for and utilization of test equipment having a precision probe and a high precision step and repeat mechanism. CPA is a method and circuit design discipline that, where followed, will result in a testable multichip package given that each logical component is testable and the design is synchronous in nature. The CPA discipline is able to accomplish this by making use of shift register latches on the chips or functional island periphery. These latches are used to indirectly observe and/or control the synchronous network, in many ways replicating the stuckfault test environment under which tests were generated at the lower subcomponent level of assembly. One method, full CPA, offers the ability to apply these tests to all full CPA chips on the multichip package simultaneously or in unison, thus reducing manufacturing tester time. An additional benefit is the ease of testing intercomponent connections.

Method of concurrently testing each of a plurality of interconnected

Chip partitioning aid (CPA)-A structure for test pattern generation for

A plurality of two stage Gray code counters are connected in series to generate a multiple bit pseudo Gray code count C.sub.0, C.sub.1, . . . , C.sub.7. A binary count B.sub.0, B.sub.1, . . . , B.sub.7 is then generated by using the odd subscripted bits C.sub.1, C.sub.3, C.sub.5, C.sub.7 of the pseudo Gray code as the binary count bits B.sub.1, B.sub.3, B.sub.5, B.sub.7 and generating the even subscripted bits of the binary count B.sub.0, B.sub.2, B.sub.4, B.sub.6 by Exclusive ORing the odd and even position counts of each two stage Gray code counter together in Exclusive OR circuits.

High speed binary counter

One of the significant features of the invention, as in U.S. Pat. No. 3,783,254, is the implementation of shift register latches as basic building blocks in a logic organization and system with combinational logic networks which provide the excitation for the shift register latches. These shift register latches in the invention as well as in the patent contain a pair of latches where one is a 'master' latch and another a 'slave'. The structure in the patent requires the 'master' and 'slave' latches to be part of the shift register for scan-in/scan-out. However, only the 'master' may be set with data from the logic system surrounding it while the 'slave' may only be set with data which previously resided in the related 'master' latch. Thus, in those logic organizations where only the 'master' latch output is required, the usefulness of the 'slave' latch is limited to scan-in/scan-out. In the shift register latch of the invention, the 'slave' latch must be set with the data that resided in the related 'master' latch during scan-in/scan-out. However, in logic systems requiring the use of only one latch of the shift register latch, both 'master' and 'slave' latches can perform independent of the other; that is, each latch may be set with data from the logic system without any influence from the other latch in the same shift register latch. Similarly, both 'master' and 'slave' may feed different sections of the logic surrounding it.

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Wappingers Falls, NY, United States of America

Sumit Dasgupta