Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Mitsubishi Jidosha Kogyo Kabushiki Kaisha

Goldstar, Co., Ltd.

Lg Electronics Inc.

Toshiba Corporation

Sumio Tanaka

Shigeru Atsumi

Nobuaki Ohtsuka

Shinji Saito

Junichi Miyamoto

Ryu Ogiwara

Daisaburo Takashima

Yukihito Oowaki

Yoshiaki Takeuchi

Mitsuru Shimizu

Keniti Imamiya

Yasuo Itoh

Katsunori Ueda

Masao Kuriyama

Hiroyuki Takenaka

Shigeyoshi Watanabe

Shigetoshi Hirano

Yumiko Iyama

Yoshihisa Iwata

Kenichi Imamiya

Takashi Mori

Hiroshi Iwahashi

Masaki Sato

Masamichi Asano

Ryo Shimizu

Toshiyuki Miyata

Nobuaki Otsuka

Yoshihisa Sugiura

Yusuke Sasaki

Koichi Kanzaki

Masazi Mito

Tatsuya Tawaki

Kenji Shibata

Yeong J Joo

Shinichi Maekawa

Yuichi Kawasaki

Nobauki Otsuka

Toshiyuki Sanko

A vehicle control apparatus includes a detection section, a control section. The detection section is configured to detect vehicle information including a vehicle speed of a vehicle driven by an electric motor and drive torque of the electric motor. The control section is configured to moderate a rate of increase in the drive torque at the time of acceleration with respect to a rate of increase set in advance on the basis of a detection result of the detection section on condition that the vehicle speed of the vehicle is less than or equal to a predetermined speed and the drive torque is greater than or equal to a predetermined threshold.

Vehicle control apparatus

An apparatus for estimating temperatures of a vehicle includes an acquirer to acquire an engine correlated temperature correlated with the temperature of an engine when the engine is stopping. The apparatus further includes an estimator to estimate a catalyst temperature of a catalyst disposed in an exhaust system of the engine, based on an inlet gas temperature estimated through a first-order lag operation with an exhaust-manifold temperature at a stop of the engine as an initial temperature and the engine correlated temperature as a target temperature.

Apparatus for estimating temperatures of vehicle

An engine operation control device for a hybrid vehicle, including: an engine provided in a vehicle; a power generator that is driven by the engine to generate electric power; a driving battery that is chargeable with electric power supplied from the power generator; and a front motor and a rear motor that drive wheels with electric power supplied from the driving battery or the power generator, and allowing a series mode in which the front motor drives front wheels and the rear motor drives rear wheels while the engine is operated at a predetermined set rotational speed to drive the power generator to generate electric power, wherein the set rotational speed is set to increase with decreasing of the atmospheric pressure in a present position of the vehicle in the series mode.

Engine operation control device for hybrid vehicle

A traveling mode switching controller of a hybrid electric vehicle has a state-of-charge detection unit; a driver request output detection unit; a correction unit; and a switching control unit for controlling a switch from a first traveling mode to a second traveling mode when a vehicle request output exceeds an output threshold value. In the first traveling mode, an engine is deactivated and the drive motor is activated. In the second traveling mode, drive wheels are actuated by means of driving power of the engine, or a generator connected to the engine is activated to generate electric power to activate the drive motor to actuate the drive wheels. The switching control unit sets the output threshold value low as the state of charge decreases, thereby changing conditions for switching the first traveling mode to the second traveling mode.

Traveling mode switching controller of hybrid electric vehicle

A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Chain ferroelectric random access memory (CFRAM) having an intrinsic transistor connected in parallel with a ferroelectric capacitor

Ferroelectric memory with an intrinsic access transistor coupled to a capacitor

A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Ferroelectric random access memory with isolation transistors coupled between a sense amplifier and an equalization circuit

Chain-type ferroelectric random access memory (FRAM) with rewrite transistors coupled between a sense amplifier and a bit line pair

In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

Nonvolatile semiconductor memory device including a circuit for providing a boosted potential

Chain type ferroelectric memory with isolation transistors coupled between a sense amplifier and an equalization circuit

Nonvolatile semiconductor memory device

A semiconductor memory device reads data corresponding to charges stored in a capacitor in a memory cell and rewrites the data. This semiconductor memory device removes charges stored in the capacitor in the memory cell to a bit line or absorbs charges stored in the bit line into the capacitor in the memory cell, thereby generating a potential difference between the bit line pair. This potential difference is sensed by a sense amplifier and rewritten. Before the sense amplifier is operated, the potential difference is generated between the bit line pair. The parasitic capacitances of the bit line pair during operation of the sense amplifier are substantially equalized, and in this state, the potential difference is sensed.

Semiconductor memory device for reading charges stored in capacitor in memory cell and data reading method thereof

A ferroelectric memory device includes a plate line driving circuit, dummy plate line driving circuit, constant voltage generator and variable voltage generating circuit. The plate line driving circuit pulse-drives a plate line associated with a memory cell selected at the time of data readout. The dummy plate line driving circuit pulse-drives a dummy plate line associated with a dummy cell connected to a reference bit line which makes a complementary pair with a bit line connected to the selected memory cell. The constant voltage generator generates a voltage which does not depend on an external power supply voltage and the temperature and is kept substantially constant and applies the voltage to the plate line driving circuit as a power supply voltage. The variable voltage generating circuit generates a plurality of substantially constant voltages which do not depend on an external power supply voltage and the temperature and applies a voltage selected from the plurality of voltage levels according to the high level or low level of the bit line to the dummy plate line driving circuit as a power supply voltage.

Ferroelectric memory device

A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during another modes.

Nonvolatile semiconductor memory device having row decoder

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Tokyo, Japan

Sumio Tanaka