Elpida Memory, Inc.

Nec Corporation

Nec Electronics Corporation

Sumio Ogawa

Shinichi Hara

Yasuji Koshikawa

Minoru Ueki

Shinichi Miyatake

An element isolation region exists at a side opposite to a diffusion layer region as seen from a channel region, without another electrode to which the same potential as one applied to the diffusion layer region is applied interposed between the channel region and the element isolation region. The electric field applied to the gate insulating film is not uniform and the magnitude of the electric field is increased when approaching closer to the diffusion layer region. Therefore, breakdown is likely to occur at parts closer to the diffusion layer region.

Semiconductor device including antifuse element

An anti-fuse circuit according to the present invention includes an anti-fuse element that holds data in a nonvolatile manner and a latch circuit that temporarily holds data to be written to the anti-fuse element. The writing to the latch circuit can be performed in the order of nanoseconds, and thus, even when the defective addresses respectively different are written in a plurality of chips, a writing process to the latch circuit can be completed in a very short period of time. Thereby, an actual process for writing to the anti-fuse element can be performed in parallel for the chips, and as a result, the process for writing to the anti-fuse element can be performed at high speed.

Semiconductor device including anti-fuse circuit, and method of writing address to anti-fuse circuit

A semiconductor device includes plural fuse elements which can be disconnected by irradiating a laser beam, and attenuation members which are located between the plural fuse elements as viewed two-dimensionally and can attenuate the laser beam. Each attenuation member includes plural columnar bodies. With this arrangement, the attenuation members including plural columnar units absorb the laser beam leaked out from a fuse element to be disconnected to a semiconductor substrate side. The laser beam is also scattered by Fresnel diffraction. Therefore, the columnar body can efficiently attenuate the laser beam, without generating a crack in the insulation film by absorbing excessive energy.

Semiconductor device including a plurality of fuse elements and attenuation members between or around the plurality of fuse elements

To provide an antifuse element comprising a gate electrode, a depletion channel region, a gate insulating film between the gate electrode and the channel region, and a diffusion layer region forming a junction with the channel region. An end of the gate electrode coincides substantially with a boundary between the channel region and the diffusion layer region as seen from a planar view, and is formed in a zigzag configuration. The end of the gate electrode is longer than the end with linear configuration and the end of the gate insulating film is likely to be subjected to breakdown.

Antifuse element and semiconductor device including same

In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired. The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A redundancy memory block which substitutes for defective data of a segment is physically provided to each of the plurality of memory blocks. A block address of the redundancy memory block is logically allocated to the plurality of memory blocks in common.

Semiconductor memory device

A semiconductor device includes a lower electrode, an upper electrode, and a fuse element that connects the lower electrode and the upper electrode. The height of the fuse element is greater than the depth of focus of a laser beam to be irradiated. The diameter of the fuse element is smaller than the diffraction limit of the laser beam. Thus, in the present invention, a vertically long fuse element is used, so that it is possible to efficiently absorb the energy of the laser beam. It is possible to cut the fuse element by using an optical system having a small depth of focus, so that the damage imposed on a member located above or below the fuse element is very small. As a result, the fuse element can be without destructing the passivation film.

Semiconductor device having fuse element arranged between electrodes formed in different wiring layers

Semiconductor storage device

In replacing word lines having defective addresses with redundant word lines, information is held in a relationship between the word lines and the redundant word lines. In other words, information is held in a replacement rule. With this arrangement, information such as a lot number, a wafer number within the lot, and a position of a chip within the wafer can be held in the chip, without increasing the chip area at all and without using a large database.

Chip information managing method, chip information managing system, and chip information managing program

A semiconductor device manufacturing system is provided in which chip position information is read without removing resin from a package so that the cause of a failure can be quickly identified and removed and the yield of chips can be rapidly improved. A replacement address reading device reads redundancy addresses from a semiconductor device which is determined as faulty in a test performed after the semiconductor device has been sealed into a package. A chip position analyzing device estimates, from the combination of these redundancy addresses, a lot number, a wafer number and a chip number of the faulty semiconductor device. A failure distribution mapping device maps the distribution of faulty chips in each wafer in the lot based on these numbers thus obtained. A failure cause determining device identifies which manufacturing device or processing step has caused the failures in the wafer process based on the above distribution.

Method of manufacturing semiconductor devices

A semiconductor memory production system is provided, capable of holding the data necessary for process analysis for each lot in chronological order using a small amount of information, and which enables production management based on data that has been stored previously without performing new measurements. The semiconductor memory production system comprises: an LSI tester that tests semiconductor memory and outputs the addresses of memory cells for each chip and a pass/fail bitmap corresponding to these addresses, and a process defect estimating device that extracts the bit addresses of fail bits from the bitmap, and determines replacement addresses of word lines and bit lines to be replaced by redundant word lines and redundant bit lines in the redundant memory section, and estimates process defects from statistical analysis of the distribution condition of each chip on each wafer. Through this estimated result, feedback to the manufacturing line/process step prevents from producing defects frequently.

Semiconductor memory production system and semiconductor memory production method

Semiconductor device manufacturing system and method of manufacturing semiconductor devices

A semiconductor memory test circuit comprises a current mirror circuit including a reference side current path composed of a series connection of alternating p channel transistors and n channel transistors and an output side current path composed of a series connection of alternating p channel transistors and n channel transistors, an output signal for electrode of paired memory cells and a balance potential output signal for sense amplifier, required for a semiconductor memory test, being derived from the output side current path. The current mirror circuit includes a first output side current path and a second output side current path, the balance output for sense amplifier is derived from an output of the first output side current path and the output signal for electrode of paired memory cells is derived from an output of the second output side current path.

Semiconductor memory test circuit

In a semiconductor memory device including a plurality of memory cell clocks each having a mormal memory cell array and first and second redundancy memory cell rows, one first redundancy row selecting circuit is provided for each of the memory cell blocks to access the first redundancy memory cell row upon receipt of a respective memory cell block selection signal, and one second redundancy row selecting circuit is provided for at least two of the memory cell blocks to access the second redundancy memory cell row upon receipt of a respective memory cell block selection signal.

Semiconductor memory device incorporating redundancy memory cells

A shared sense amplifier circuit incorporated in a dynamic random access memory device is coupled at input/output nodes with dummy cells implemented by n-channel enhancement type field effect transistors for pulling one of the input/output nodes down upon access to one of the memory cells, and one of the enhancement type dummy cells rapidly turns off so that undershoot takes place at the associated input/output node due to channel resistance between the shared sense amplifier circuit and a bit line pair, thereby enlarging differential voltage applied between the input/output nodes of the shared sense amplifier circuit.

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Tokyo, Japan

Sumio Ogawa