Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Kioxia Corporation

Sumio Kuroda

Yoshihisa Kojima

Katsuhiko Ueki

Kazutaka Takizawa

Masaaki Niijima

Yasuyuki Ozawa

Yuji Sakai

Kazuhito Shimomura

Kenichiro Suzuki

Kouichi Ogi

According to one embodiment, a memory system includes a first memory and a memory controller. The first memory is nonvolatile and includes a plurality of memory cell transistors, each of which stores data corresponding to a threshold voltage. The memory controller causes the first memory to execute a read operation to acquire data corresponding to the threshold voltage from the plurality of memory cell transistors on the basis of a result of comparison between the threshold voltage and a read voltage. The memory controller selects a first candidate value from among a plurality of candidate values for the read voltage in accordance with a degree of stress that affects the threshold voltage; and causes the first memory to execute the read operation using the first candidate value as the read voltage.

Memory system controlling a threshold voltage in a read operation and method

A memory system includes a plurality of memory cells and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. During a read operation to read data from the memory cells, the controller decodes second data read from the memory cells at the first code rate. The controller changes the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a threshold number for error bits or upon determining that the number of memory cells having a threshold voltage that is in a voltage range that includes a read voltage is above a threshold number for memory cells.

Memory system and method

A memory system includes a memory that includes a plurality of memory cells, and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. During a read operation to read data from the memory cells, the controller decodes second data read from the memory cells at the first code rate. The controller changes the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a threshold number for error bits or upon determining that the number of memory cells having a threshold voltage that is in a voltage range that includes a read voltage is above a threshold number for memory cells.

Memory system and method for controlling code rate for data to be stored

According to one embodiment, a control system includes: a memory device; and a controller. The memory device includes a first cell transistor. The controller is configured to store information on a first temperature associated with a temperature of the memory device upon a write of data in the first cell transistor, obtain a second temperature of the memory device, determine an adjustment from adjustments based on a combination of the first temperature and the second temperature, and instruct the memory device to use for a first parameter a first value and a value which is based on the determined adjustment to read data from the first cell transistor.

Control system

According to one embodiment, an information recording apparatus includes a divider, a generator, and a recorder. The divider is configured to divide recording data into a plurality of recording data blocks for each predetermined recording unit. The generator is configured to set, as a first block set, n recording data blocks recorded in corresponding areas in file system management areas of n, first to nth (n: integer, n&#x2267;2) storages, and generate first parity data from the n recording data blocks forming the first block set. The recorder is configured to record the n recording data blocks forming the first block set and the first parity data.

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Yokohama Kanagawa, Japan

Sumio Kuroda