Seiko Instruments Inc

Sumio Koiwa

Jun Osanai

Kenji Kitamura

Hisashi Hasegawa

Kazutoshi Ishii

A semiconductor device has a semiconductor circuit provided on a semiconductor substrate. The semiconductor circuit has a source, a drain, a gate and a wiring connected to one of the source, the drain and the gate. Conductors for electrostatic discharge protection are connected to one of a ground line and a power supply line and are disposed over a region of the semiconductor circuit not occupied by the wiring. A ratio of a total area of the conductors disposed over the semiconductor circuit to an area of a chip occupied by the semiconductor circuit is 40% or more.

Semiconductor device and designing method for the same

A photodiode comprises an optical detection portion for detecting an optical signal and outputting a photoelectric conversion signal. The optical detection portion has a semiconductor substrate of a first conductive type and semiconductor layers of a second conductive type formed in spaced-apart relation in a surface of the semiconductor subtrate. A depletion layer is formed in the semiconductor subtrate by application of a reverse bias to the photodiode so as to surround the semiconductor layers. An etched surface portion of the depletion layer is disposed between the semiconductor layers so that an interface level region of the surface of the semiconductor substrate does not exist between the semiconductor layers.

Short-wavelength photodiode of enhanced sensitivity with low leak current and method of manufacturing photodiode

In a power management semiconductor device or analog semiconductor device having a CMOS and a resistor, a conductivity type of a gate electrode of the CMOS is P-type as to both an NMOS and a PMOS, a short channel and a low threshold voltage are possible since an E-type PMOS is surface channel type, the short channel and the low threshold voltage are possible since a buried channel type NMOS is extremely shallow for the reason that arsenic having a small diffusion coefficient can be used as an impurity for threshold control, and the resistor used in a voltage dividing circuit or CR circuit is formed of polycrystalline silicon thinner than the polycrystalline silicon of the same layer as the gate electrode or a thin film metal. Thus, the power management semiconductor device or analog semiconductor device, which is advantageous in terms of cost, manufacturing period and element performance in comparison with the conventional CMOS with an N&plus;polycrystalline silicon gate single polarity or the same polarity gate CMOS in which a channel and a gate electrode have the same polarity, can be realized.

Complementary MOS semiconductor device

To provide a method of manufacturing a semiconductor device in which an epitaxial growth film is formed on a semiconductor substrate having a buried layer, which is capable of reducing the manufacturing time of the semiconductor device or reducing the IC chip area. The method of manufacturing a semiconductor device is characterized by including a process of selecting the concentration of the p-type conductive impurities which put the surface of the silicon semiconductor substrate into a full amorphous state and conducting doping with the impurities.

Method of manufacturing a semiconductor device

A MOS semiconductor device comprises a semiconductor substrate having source and drain regions, a first insulating film disposed over the substrate in a space overlapping opposed edges of the source and drain regions, and a gate electrode disposed on the first insulating film. A second insulating film is disposed at overlapping portions between the gate electrode and the source and drain regions to prevent the formation of a space therebetween.

Growing community of inventors

Chiba, Japan

Sumio Koiwa