Hitachi, Ltd.

Other

Sumio Kikuchi

Hiroyasu Nishiyama

Takayoshi Iitsuka

Akira Nishimoto

Yo Nonomura

Kyoko Iwasawa

Hiroshi Ohta

Takeshi Horiuchi

Noriyasu Mori

Keiko Motokawa

Takashi Kurosawa

Yooichi Takeuchi

Takashi Hirooka

When converting a sequential execution source program into a parallel program to be executed by respective processors (nodes) of a distributed shared memory parallel computer, a compiler computer transforms the source program to increase a processing speed of the parallel program. First, a kernel loop having a longest sequential execution time is detected in the source program. Next, a data access pattern equal to that of the kernel loop is reproduced to generate a control code to control first touch data distribution. The first touch control code generated is inserted in the parallel program.

Parallel program generating method

The present invention provides a memory access optimizing method which judges an access method suitable for each of memory accesses and executes the preload optimization and prefetch optimization, according to the judgement result, for an architecture equipped with a prefetch mechanism to write the data on a main storage device into a cache memory and a preload mechanism to write the data on the main storage device into a register without writing it into the cache memory. The memory access method judging step analyzes whether or not there is a designation of a memory access method by a user. Moreover, the memory access method judging step investigates whether or not the data are already in a cache memory, whether or not the data compete with other data for a cache, whether or not the data are to be referred to again later, and whether or not the data fulfill the restriction on register resources.

Memory access optimizing method

A branch predictor for predicting an instruction to be executed next to a conditional branch instruction in a program to read the predicted instruction beforehand. The branch predictor includes a hint acquisition section for acquiring a hint when a specified instruction controlling acquisition of the hint is executed wherein said hint indicates whether a branch is to be taken by execution of a conditional branch instruction with which termination of a loop is judged. The branch predictor further includes a hint store section for storing the hint acquired by the hint acquisition section, and an instruction read section for reading an instruction predicted as executed next to a conditional branch instruction in accordance with the hint stored in the hint store section. According to the invention it is possible to accurately predict a branch at the time of loop termination of the loop termination judging conditional branch instruction.

Branch predictor

In order to generate a source program or an object code which can be executed in parallel efficiency by detecting an independent operation of a large grain size from a program which can not be analyzed by the compiler, a parallelization supporting tool inputs a result of an output of the interprocedural analyzer,and the source program. A program of intermediate language is produced by the parse and the program of information of common and dummy argument variables is reflected into the program of intermediate language by the interprocedural variable information read processing. After a control flow analysis and a dataflow analysis have been carried out, dependency unknown variables are extracted and parallelizability conditions are produced. Based on the result of the produced conditions, questions and answers are made with the user or a condition statement is inserted into the source program to execute the program and a decision of parallelizability is made. A source program or a parallelized object program which has been corrected in accordance with a user's request is also produced.

Method for supporting parallelization of source program

Prefetch instructions having a function to move data to a cache memory from main memory are scheduled simultaneously with execution of other instructions. The prefetch instructions are scheduled by replacing, with the original prefetch instructions, the virtual prefetch instructions obtained by unrolling a kernel section of the schedule constituted by generating a dependency graph having dependent relationships between the prefetch instruction and the memory reference instruction, and then applying the software pipelining thereto, or by further unrolling the kernel section of the constituted schedule to delete the redundant prefetch instructions, or further by applying the software pipelining to the dependency graph which is formed by combining a plurality of prefetch instructions and replacing the prefetch instructions with virtual prefetch instructions.

Method for compiling loops containing prefetch instructions that

In a processor system including a plurality of hardware resources, a method for arranging a program to suppress the power consumption by the resources includes the steps of determining which ones of the hardware resources are to be operated and from which instruction cycle to which instruction cycle to execute each instruction of the program; and based on the determination, adding an instruction to lower frequencies of clock signals inputted to the hardware resources and an instruction to restore the frequency at positions adjacent to the beginning and the end of the period during which the hardware resources are not operated and compiling the program. The processor system decodes the compiled program and lowers the frequency of the clock signal inputted to the hardware resources in accordance with the frequency lowering instruction and the frequency restoring instruction detected in the decoding step. The clock signals sent to the hardware resources are stopped by the frequency lowering instruction to the resource of the hardware resources for which the clock frequency may be lowered to zero.

Method for controlling a processor for power-saving in a computer for

A method and apparatus for analyzing a DO-statement to determine the type of a DO-variable and for determining whether a sign of an incrementation parameter at the time of compile can be determined are provided in a DO-loop object code generator in a compiler to select an object code generating method corresponding to the state of the DO-loop. As a result, object codes fitted to each DO-loop are generated which are so efficient as to improve the iteration count according to the ANSI standard, saving of use of registers, elimination of unnecessary calculation and the like.

Method and apparatus for compiling a program incending a do-statement

A method of testing a source program includes the steps of converting the source program into a load module while dividing statements of the source program associated with access to same data into a plurality of processes, executing the load module while generating access information representing a process defining the data or a process using the data each time the data is accessed, and determining in accordance with said access information whether or not the using process coincides with the defining process or whether or not the use by the using process precedes the definition by the defining process.

Method of testing program, and compiler and program testing tool for the

A program compiling method in which a procedure being compiled is split into a plurality of units referred to as segments, whereon optimization is carried out for each of the segments. Upon recompilation of the procedure, optimization of the procedure is redone not for the whole of the procedure but executed only on the segments which are affected by modification, while for the segments insusceptible to the influence of modification, object program obtained by the compilation or the intermediate codes available in the course of the optimization are reused. At several stages of optimization, intermediate results of the optimization are recorded, wherein upon recompilation, the intermediate results of optimization obtained in the preceding compilation are made use of up to the stage where no influence of modification makes appearance. The amount of processing involved in the optimization can thus be reduced even when the object program can not be utilized. In a mode for carrying out the invention, not only the interim results of optimization but also the contents of optimization executed are recorded. Upon recompilation, those of the optimization processings executed in the preceding compilation which are to be executed again can be performed rapidly by making use of the contents stored. The time taken for the execution of optimization processing to be re-executed can be reduced significantly.

Method of recompiling a program by using result of previous compilation

A compile method to be executed in a digital computer includes the step for detecting among statements in source program codes a first statement defining a first variable and including a polynomial of a plurality of other variables to define the first variable and a second statement including the first variable defined by the first statement so as to use the first variable. The method also includes the steps of judging whether or not the detected second statement satisfies a predetermined copy propagation condition and of replacing the first variable included in the second statement, when a result of the judgement indicates the condition to be satisfied by the second statement, with the polynomial and for eliminating the first statement, with the polynomial anbd for eliminating the first statement. Finally, the method includes the step of generating from a source code after the replacing step object program codes corresponding to the source code.

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Machida, Japan

Sumio Kikuchi