Sharp Kabushiki Kaisha Corporation

Sumio Katoh

Naoki Ueda

Hidehito Kitakado

Tadayoshi Miyamoto

Seiichi Uchida

Fumiki Nakano

Kuniaki Okada

Kazuhide Tomiyasu

Tokuaki Kuniyoshi

A semiconductor device includes: a first metal layer including a gate electrode; a first insulating layer provided on the first metal layer; an oxide semiconductor layer provided on the first insulating layer; a second insulating layer provided on the oxide semiconductor layer; a second metal layer provided on the oxide semiconductor layer and the second insulating layer, the second metal layer including a source electrode; a third insulating layer provided on the second metal layer; and a first transparent electrode layer provided on the third insulating layer. The oxide semiconductor layer includes a first portion lying above the gate electrode and a second portion extending from the first portion so as to lie across an edge of the gate electrode on the drain electrode side. The third insulating layer does not include an organic insulating layer. The second insulating layer and the third insulating layer have a first contact hole which overlaps the second portion of the oxide semiconductor layer when viewed in a normal direction of the substrate. The first transparent electrode layer includes a transparent electrically-conductive layer which is in contact with the second portion of the oxide semiconductor layer in the first contact hole.

Semiconductor device, liquid crystal display device, and semiconductor device manufacturing method

A semiconductor device (A) includes a thin film transistor (), an inter-layer insulation layer () covering the thin film transistor, and a transparent conductive layer () formed on the inter-layer insulation layer. The metal oxide layer () of the thin film transistor includes a first portion () overlapping the gate electrode () via a gate insulation layer () and a second portion () not overlapping the gate electrode (). The second portion () crosses a different edge (e) different from an edge (e) of the drain electrode () on a side of the first portion when viewed in the normal direction of the substrate (). The inter-layer insulation layer has a contact hole () disposed to overlap a part of the drain electrode () and at least a part of the second portion () of the metal oxide layer when viewed in the normal direction of the substrate. The transparent conductive layer () comes into contact with the drain electrode (), the second portion (), and the gate insulation layer () in the contact hole ().

Semiconductor device, display apparatus, and method of manufacturing semiconductor device

A semiconductor device includes a TFT (), the TFT including a gate electrode (), a gate insulating layer () covering the gate electrode, a metal oxide layer (A) including a channel region (), a source contact region () and a drain contact region (), a first electrode (A) in contact with the source contact region, an insulating layer () formed on the metal oxide layer and the first electrode, the insulating layer having a first opening () therein through which a portion of the metal oxide layer is exposed, and a light-transmissive second electrode () formed on the insulating layer and in a contact hole including the first opening, wherein the second electrode () is in contact with the drain contact region () in the contact hole, the drain contact region () is a portion of a region () of the metal oxide layer (A) that is exposed through the contact hole, and as seen from a direction normal to a substrate (), the second electrode () does not overlap the channel region ().

Semiconductor device and method for manufacturing same

A semiconductor device () includes: a memory cell; and a writing control circuit (), wherein the memory cell includes a memory transistor (A) which has an active layer (A), the active layer (A) including a metal oxide, the memory transistor (A) is a transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Ids depends on a gate-source voltage Vgs to a resistor state where the drain current Ids does not depend on the gate-source voltage Vgs, and the writing control circuit () is configured to control voltages applied to a drain electrode, a source electrode and a gate electrode such that Vgs&#x2267;Vds+Vth is satisfied where Vth is a threshold voltage of the memory transistor (A) and Vds is a drain-source voltage of the memory transistor (A), whereby writing in the memory transistor (A) is performed.

Semiconductor device and method for writing thereto

A semiconductor device () includes: a first transistor (A) having a first channel length Land a first channel width W; and a second transistor (B) having a second channel length Land a second channel width W, wherein the first transistor (A) and the second transistor (B) include an active layer formed from a common oxide semiconductor film, the first transistor (A) is a memory transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Isd depends on a gate voltage Vg to a resistor state where the drain current Isd does not depend on the gate voltage Vg, and the first channel length Lis smaller than the second channel length L

Semiconductor device with U-shaped active portion

A semiconductor device includes a memory transistor (A) which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg. The memory transistor (A) includes a gate electrode (), a metal oxide layer (), a gate insulating film (), and source and drain electrodes. The drain electrode (d) has a multilayer structure which includes a first drain metal layer (d) and a second drain metal layer (d), the first drain metal layer (d) being made of a first metal whose melting point is not less than 1200&#xb0; C., the second drain metal layer (d) being made of a second metal whose melting point is lower than that of the first metal. Part P of the drain electroded extends over both the metal oxide layer () and the gate electrode () when viewed in a direction normal to a surface of the substrate. The part (P) of the drain electrode (d) includes the first drain metal layer (d) and does not include the second drain metal layer (d).

Semiconductor device

A semiconductor device (A) includes a first metal layer () including a gate electrode (); a gate insulating layer () formed on the first metal layer; an oxide semiconductor layer () formed on the gate insulating layer; a second metal layer () formed on the oxide semiconductor layer; an interlayer insulating layer () formed on the second metal layer; and a transparent electrode layer (TE) including a transparent conductive layer (Tc). The oxide semiconductor layer includes a first portion () and a second portion () extending while crossing an edge of the gate electrode. The second metal layer includes a source electrode () and a drain electrode (). The interlayer insulating layer does not include an organic insulating layer. The interlayer insulating layer includes a contact hole () formed so as to overlap the second portion and an end of the drain electrode that is closer to the second portion. The transparent conductive layer (Tc) is in contact with the end of the drain electrode and the second portion of the oxide semiconductor layer in the contact hole.

Semiconductor device, display device, and method for manufacturing semiconductor device

A memory cell () includes a memory transistor (A) having channel length Land channel width W, and a plurality of select transistors (B) each electrically being connected in series with the memory transistor and independently having channel length Land channel width W, wherein each of the memory transistor and the plurality of select transistors includes an active layer (A) formed from a common oxide semiconductor film, the memory transistor is a transistor which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg, and channel length Lis greater than channel length L

The present invention provides a non-volatile memory device using a memory transistor including an oxide semiconductor, capable of writing with low power consumption, without receiving an influence of deterioration of a selection transistor connected in series to the memory transistor. A memory cellincludes a memory transistor Qm, and first and second selection transistors Qand Q. During a writing operation, the memory transistor Qm and the first selection transistor Qare set to the ON state, and the second selection transistor Qis set to the OFF state. A writing current is flown to a series circuit of the memory transistor Qm and the first selection transistor Q. The memory transistor Qm is transited from a first state that indicates a transistor characteristic to a second state that indicates an ohmic resistance characteristic. During a reading operation, the first selection transistor Qis set to the OFF state, the second selection transistor Qis set to the ON state, a voltage is applied to a series circuit of the memory transistor Qm and the second selection transistor Q, and it is detected whether the memory transistor Qm is in the first state or the second state.

Non-volatile memory device

The invention provides a thin film transistor that can reduce an off-current flowing in end-parts in a channel width direction of a channel layer and a manufacturing method therefor.

Thin film transistor and display device

In a thin film transistor substrate () having an island-like channel protection layer () covering a channel portion of an oxide semiconductor layer (), a source electrode (S) and a drain electrode (D) are formed of an aluminum alloy film or a multilayer film including an aluminum alloy film.

Thin film transistor substrate, display device, and method for manufacturing thin film transistor substrate

A semiconductor device (S) includes a substrate (), a gate electrode (), a gate insulating film (), an oxide semiconductor film () including a channel part () formed in a position facing the gate electrode (), a source electrode (), and a drain electrode (). The source electrode () and the drain electrode () is arranged so as not to overlap with the gate electrode () as viewed in the plane. A region adjacent to the gate electrode () and the source electrode () and a region adjacent to the gate electrode () and the drain electrode () are, in a region where the source electrode () and the drain electrode () does not overlap with the gate electrode (), processed such that resistance in a region of the oxide semiconductor film () including a surface thereof is reduced.

Thin film transistor including semiconductor oxide layer having reduced resistance regions

The invention provides a thin film transistor having current driving force that can be substantially improved. By heat treatment, the IGZO layer () from which oxygen is taken away by the titanium electrodes () becomes the low resistance regions (), and the IGZO layer () from which oxygen is not taken away remains as the high resistance region (). In this state, when the gate voltage is applied to the gate electrode (), electrons in the low resistance regions () near the boundaries with the high resistance region () move respectively to the titanium electrode () sides. As a result, the length of the low resistance regions () becomes short, and oppositely, the length of the high resistance region () becomes longer by the size of the shortened low resistance regions. However, the electrical channel length (Le) becomes shorter than the source/drain interval space (Lch) as the limit resolution of the exposure device, and the current driving force becomes large.

Provided is a thin film transistor manufacture method by which a thin film transistor provided with LDD regions can be produced without increasing the number of photo masks used. An etching stopper layer () formed on a polycrystalline silicon film () of a TFT () is used not only as a mask to protect a channel region () when a source electrode and a drain electrode are formed by etching, but also as a mask when ions are implanted to form a source/drain regions (). Thus, phosphorus, which is ion-implanted in the polycrystalline silicon film () to form the source/drain regions (), is not implanted in the LDD region () and, accordingly, it is not necessary to additionally form a resist pattern to be used as a mask when ions are implanted.

Growing community of inventors

Osaka, Japan

Sumio Katoh