Halo Microelectronics International

Nxp B.v.

Halo Microelectronics Co., Ltd.

Suming Lai

Kenneth Chung-Yin Kwok

Fuchun Zhan

Kien Chan Vi

Kenneth Chung Yin Kwok

Songnan Yang

Lijie Zhao

Jian Qing

Zhao Fang

Xuechu Li

Anan Xiang

A method includes connecting an output of a switched capacitor converter to a battery, the switched capacitor converter comprising a first switch, a second switch, a third switch and an upper circuit connected in series, and a flying capacitor connected between a common node of the first switch and the second switch, and a common node of the third switch and the upper circuit, in a first short circuit testing step, determining whether the third switch is shorted by comparing a voltage on the common node of the third switch and the upper circuit with a first predetermined voltage reference, and in a second short circuit testing step, determining whether the first switch and the second switch are shorted by comparing a voltage on the common node of the first switch and the second switch with a second predetermined voltage reference and a third predetermined voltage reference, respectively.

Short circuit detection apparatus and control method for switched capacitor converter

An apparatus includes a first drain/source region and a second drain/source region surrounded by an isolation ring formed over a substrate, the isolation ring formed being configured to be floating, and a first diode connected between the substrate and the isolation ring, wherein the first diode is a Schottky diode.

Latch-up free high voltage device

The present disclosure provides a transistor, a method for configuring the same, an electrostatic discharge (ESD) protection circuit, and an electronic device for ESD protection. The transistor comprises a P-type well, a body terminal region, a source region, and a metal silicide layer. The body terminal region and the source region are disposed within the P-type well. The body terminal region is adjacent to the source region. The metal silicide layer is disposed on surfaces of the body terminal region and the source region, and electrically connected to the body terminal region and the source region separately. A metal and contact structures are provided on the metal silicide layer to adjust the resistance between the emitter of the parasitic bipolar transistor of the transistor and the body terminal region or between the base of the parasitic bipolar transistor and the source region, for ESD protection.

Transistors, method for making the same, electrostatic discharge protection circuit, and electronic device

A power converter includes a plurality of power switches connected in series between a system ground and an input voltage bus, wherein an upper power switch located between the input voltage bus and an output terminal of the power converter, and immediately adjacent to the output terminal of the power converter is configured as an isolation switch including two back-to-back connected diodes and a bulk terminal, and wherein a connection of the bulk terminal is reconfigurable, and a driver configured to drive the upper power switch immediately adjacent to the output terminal of the power converter.

Gate drive apparatus and control method for switched capacitor converter

A method includes connecting an input voltage bus of a switched capacitor converter to a power source through a load switch, in a first short circuit testing step, determining whether the load switch or a second switch is shorted by comparing a voltage on the input voltage bus with a first predetermined voltage reference, after passing the first short circuit testing step, in a second short circuit testing step, determining whether a first switch or a fourth switch is shorted by comparing a voltage on the common node of the third switch and the fourth switch with a second predetermined voltage reference, and after passing the second short circuit testing step, in a third short circuit testing step, determining whether a third switch is shorted by comparing the voltage on the common node of the third switch and the fourth switch with a third predetermined voltage reference.

An apparatus includes a first gate drive transistor and a second gate drive transistor connected in series, a common node of the first gate drive transistor and the second gate drive transistor connected to a gate of a power switch, the second gate drive transistor configured as a bulk switch having a bulk terminal connected to a bulk terminal of the power switch, a first auxiliary transistor connected between the bulk terminal and a source of the power switch, a second auxiliary transistor coupled between the gate of the power switch and a system ground, and a third auxiliary transistor coupled between a logic control ground and the system ground, wherein the second auxiliary transistor and the third auxiliary transistor are configured to pull the gate of the power switch and the logic control ground down to the system ground in response to a turn off of the apparatus.

An example method includes controlling a switching order of a plurality of power switches. The power switches are coupled to a flying capacitor and include parasitic bipolar transistors susceptible to the voltage overstress in response to excess stray inductance of the flying capacitor. The method further includes, in response to the controlled switching order, converting an input voltage of a first voltage level to an output voltage of a second voltage level while mitigating the voltage overstress of the parasitic bipolar transistors of the plurality of power switches.

Controlling a switching order of power switches for mitigating voltage overstress

Aspects of the present disclosure are directed to circuitry to control a gate voltage. As may be implemented in accordance with one or more embodiments, a voltage level is controlled for a field effect transistor (FET) having a floating gate and a target operating voltage above which the FET would be overcharged and around which the FET has a nominal operating range. Pulse circuitry is configured to apply energy to the floating gate in pulses, in operation the applied energy being pulsed low relative to the gate's target operating voltage, and then being changed by adjusting successive pulses until the gate reaches the target operating voltage. A feedback circuit samples a voltage level of, and enables the pulse circuitry to apply pulsed energy to, the floating gate for directing operation of the FET based on the target operating voltage in the nominal operating range.

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San Diego, CA, United States of America

Suming Lai