Qualcomm Incorporated

Advanced Micro Devices Corporation

Sumesh Udayakumaran

Chihong Zhang

Andrew Evan Gruber

Babak Forutanpour

Yun Du

Alexei Vladimirovich Bourd

Maxim V Kazakov

Lin Chen

Chunhui Mei

Wolfgang Frank

Se Jong Oh

Wolfgang G Frank

Described herein are techniques for generating a stitched shader program. The techniques include identifying a set of shader programs to include in the stitched shader program, wherein the set includes at least one multiversion shader program that includes a first version of instructions and a second version of instructions, wherein the first version of instructions uses a first number of resources that is different than a second number of resources used by the second version of instructions. The techniques also include combining the set of shader programs to form the stitched shader program. The techniques further include determining a number of resources for the stitched shader program. The techniques also include based on the determined number of resources, modifying the instructions corresponding to the multiversion shader program to, when executed, execute either the first version of instructions, or the second version of instructions.

Multi-version shaders

Techniques for allowing for concurrent execution of multiple different tasks and preempted prioritized execution of tasks on a shader processor. In an example operation, a driver executed by a central processing unit (CPU) configures GPU resources based on needs of a first 'host' shader to allow the first shader to execute 'normally' on the GPU. The GPU may observe two sets of tasks, &#x201c;guest&#x201d; tasks. Based on, for example, detecting an availability of resources, the GPU may determine a &#x201c;guest&#x201d; task may be run while the &#x201c;host&#x201d; task is running. A second &#x201c;guest&#x201d; shader executes on a GPU by using resources that were configured for the first &#x201c;host&#x201d; shader if there are available resources and, in some examples, additional resources are obtained through software-programmable means.

Resource sharing on shader processor of GPU

In one example, a method includes responsive to receiving, by a processing unit, one or more instructions requesting that a first value be moved from a first general purpose register (GPR) to a third GPR and that a second value be moved from a second GPR to a fourth GPR, copying, by an initial logic unit and during a first clock cycle, the first value to an initial pipeline register, copying, by the initial logic and during a second clock cycle, the second value to the initial pipeline register, copying, by a final logic unit and during a third clock cycle, the first value from a final pipeline register to the third GPR, and copying, by the final logic unit and during a fourth clock cycle, the second value from the final pipeline register to the fourth GPR.

Utilizing pipeline registers as intermediate storage

This disclosure describes techniques for allocating registers in a computing system that supports vector physical registers. The techniques for allocating registers may allocate physical registers to vector virtual registers based on priority information that is indicative of a relative importance of allocating respective vector virtual registers as vectors rather than scalars. The techniques for allocating registers may involve allocating physical registers to the vector virtual registers in an order that is determined based on the priority information. The techniques for allocating registers may further involve, in response to determining that no vector physical registers are available to assign to a vector virtual register, determining whether to perform vector-scalar live interval splitting for the vector virtual register, spill other register live intervals into a memory in order to allocate the vector virtual register as a vector, or assign scalar physical registers to the vector virtual register based on the priority information.

Register allocation for vectors

In general, aspects of this disclosure describe a compiler for allocation of physical registers for storing constituent scalar values of a non-scalar value. In some example, the compiler, executing on a processor, may receive an instruction for operation on a non-scalar value. The compiler may divide the instruction into a plurality of instructions for operation on constituent scalar values of the non-scalar value. The compiler may allocate a plurality of physical registers to store the constituent scalar values.

Register allocation for graphics processing

A new computer-compiler architecture includes code analysis processes in which loops present in an intermediate instruction set are transformed into more efficient loops prior to fully executing the intermediate instruction set. The compiler architecture starts by generating the equivalent intermediate instructions for the original high level source code. For each loop in the intermediate instructions, a total cycle cost is calculated using a cycle cost table associated with the compiler. The compiler then generates intermediate code for replacement loops in which all conversion instructions are removed. The cycle costs for these new transformed loops are then compared against the total cycle cost for the original loops. If the total cycle costs exceed the new cycle costs, the compiler will replace the original loops in the intermediate instructions with the new transformed loops prior to generation of final code using the instruction set of the processor.

Loop transformation for computer compiler optimization

A method and system for calculating savings routes for display on a portable computing device (PCD) are described. The method includes receiving at least one of a product category and a service category from an operator of a PCD. The PCD may also receive a destination address. With this information, circle of influence data based on an offer for at least one product or service corresponding to the product category or service category may be generated and provided to the PCD. The circle of influence data may impact edge weights of a graph search algorithm. The graph search algorithm solves a single-source shortest path problem for a graph with non-negative edge path costs. The circles of influence in combination with the graph search algorithm allow a PCD to calculate one or more savings routes based on a start point and the desired destination address provided by the operator of the PCD.

Growing community of inventors

San Diego, CA, United States of America

Sumesh Udayakumaran