The Penn State Research Foundation

Sumeet Kumar Gupta

Suman Datta

Vijaykrishnan Narayanan

Xueqing Li

John Sampson

Sumitha George

Ahmedullah Aziz

Nikhil Shukla

Kaisheng Ma

A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.

Low power sense amplifier based on phase transition material

Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I&#x2212;Vhysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two Istates at V=0.

Nonvolatile digital computing with ferroelectric FET

Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I-Vhysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two Istates at V=0.

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State College, PA, United States of America

Sumeet Kumar Gupta