Texas Instruments Corporation

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Sumantra Seth

Sujoy Chakravarty

Somasunder Kattepura Sreenath

Vikram Sharma

Jagdish Chand Goyal

Anurag Arora

Geet Govind Modi

Rama Santosh Neelim Kumar Kattamuri

Subhashish Mukherjee

Raghu Ganesan

Biman Chattopadhyay

Alan Erik Segervall

Gururaj Ghorpade

Ashwin Ramachandran

Jayesh Gangaprasad Wadekar

Ross Anthony Pimentel

Abhijith Arakali

Isha Khandelwal

Baher S Haroun

Prakash Easwaran

Ravi Mehta

Rajavelu Thinakaran

Subrato Roy

Shankar Ramakrishnan

Gaurav Chandra

Saravanakkumar Swaminathan Radhakrishnan

Kalpesh Laxmanbhai Rajai

Srijan Rastogi

Sneha Teresa Thomas

Kanan Saurabh

Ankush Goel

Hariharan Nagarajan

Deepak Verma

Uttam Kumar Patro

Bharathi Rahuldev Holla

Soumyajit Roul

Arakali Abhijith

Kartik Reddy

A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

Variable reference clock signal for data transmission between PHY layer and MAC layer

A driver system includes a non-inverting system input, an inverting system input, a non-inverting system output and an inverting system output. The driver system includes a line driver which includes a non-inverting driver input coupled to the non-inverting system input and includes an inverting driver input coupled to the inverting system input. The line driver includes an inverting driver output and a non-inverting driver output. The driver system includes a first termination resistor coupled between the non-inverting driver output and the non-inverting system output and includes a second termination resistor coupled between the inverting driver output and the inverting system output. The driver system includes a first amplifier stage coupled to the line driver and includes a second amplifier stage coupled to the line driver.

Driver system for reducing common mode noise due to mismatches in differential signal path

A physical layer transceiver and a network node including the transceiver. The transceiver includes a media independent interface, a converter circuit block comprising circuitry configured to convert digital signals to analog signals for transmission over a network communications medium and convert analog signals received over the medium to digital signals, and one or more processing blocks configured to process digital data communicated between the media independent interface and the converter circuit block according to a network protocol. Management and control circuitry including power management circuitry and reset circuitry are provided. The transceiver further includes at least one single event effect (SEE) monitor, such as an ambience monitor, a configuration register monitor, a state machine monitor, or a phase locked loop (PLL) lock monitor, configured to detect and respond to an SEE event in the transceiver.

Network physical layer transceiver with single event effect detection and response

An integrated circuit includes an inverter, first and second capacitors, a resistor, and a transistor. The inverter has an input and an output. The first capacitor is coupled to a ground. The transistor has a first transistor terminal, a second transistor terminal, and a control input. The first transistor terminal is coupled to the first capacitor and the second transistor terminal is coupled to the input of the inverter. The second capacitor is coupled between the output of the inverter and the ground. The resistor is coupled between the output of the inverter and the first transistor terminal.

Voltage tolerant oscillator with enhanced RF immunity performance

Structures and methods for adjusting a reference clock based on data transmission rate between PHY and MAC layers

A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.

Interleaving ADC error correction methods for Ethernet PHY

A wakeup circuit includes an energy detection circuit and a wakeup signal generation circuit coupled to the energy detection circuit. The energy detection circuit is configured to, in response to receiving an input signal, generate a detect signal that is proportional to the input signal. The energy detection circuit is powered by the input signal. The wakeup signal generation circuit is configured to, in response to receiving the detect signal, generate a wakeup signal.

Signal powered energy detect and wakeup system

As an example, a circuit is provided. The circuit includes an ESD (electrostatic discharge) clamping circuit with a control signal controlling clamping operations of the ESD clamping circuit. The circuit further includes a counter coupled to the control signal of the ESD clamping circuit. The counter produces a set of output signals responsive to the control signal. The circuit also includes a communications interface for coupling to the set of output signals of the counter. The communications interface also couples to communications circuitry external to the circuit.

Integrated ESD event sense detector

Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels.

Low voltage feedforward current assist ethernet line driver

A line driver circuit includes a first input terminal, a second input terminal, a first input stage, a second input stage, a first output stage, and a second output stage. The first input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The second input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The first output stage includes a first input coupled to a first output terminal of the first input stage and a second input coupled to a first output terminal of the first input stage. A second output stage includes a first input coupled to a second output terminal of the first input stage and a second input coupled to a second output terminal of the first input stage.

Line driver circuit

A wakeup circuit includes an amplification stage circuit and a filter stage circuit. The amplification stage circuit is configured to, in response to receiving an input signal, generate an amplified digital signal that is proportional to the input signal. The filter stage circuit is configured to, in response to receiving a threshold number of toggles of the amplified digital signal within a pre-defined time period (such as one clock period of a clock signal), generate a wakeup signal as an output signal of the filter stage circuit.

Low power energy detector

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Bengaluru, India

Sumantra Seth