International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Sumanta Kumar Bahali

Jimmy Grant Foster, Sr

Gregory David Sellman

Warren D Bailey

John K Langgood

Juan Q Hernandez

Vinod Kamath

Paul Andrew Wormsbecher

Sumeet Kochar

Tony Carl Sass

Jeffrey Ross Hamilton

Kevin Michael Reinberg

Challis Llewellyn Purrington

Kevin S D Vernon

Tu T Dang

Michael Charles Elles

Michael Leo Scollard

Ivan R Zapata

Peter Robert Seidel

Kevin S Vernon

Brian E Bigelow

Jimmy G Foster

Dwayne A Lowe

An apparatus for memory management a high-speed fabric controller and a memory controller connected between a high-speed memory and a processor. The memory controller is configured to control processor access to the high-speed memory over a memory bus between the processor and the high-speed memory. The apparatus includes a high-speed data connection between the memory controller and the high-speed fabric controller and a data connection between a tier of persistent data storage and the high-speed fabric controller. The high-speed fabric controller is configured to control data transfers between the tier of persistent data storage over and the high-speed memory independent of the processor.

Controlling data transfers between a tier of persistent data storage and processor memory with a high-speed fabric controller

A computing system includes a processor that has a processor cache built-in, and a non-volatile memory, such as a non-volatile dual-inline memory module (NVDIMM), which is being used as system memory within the computing system. The processor processes a transaction. If the computing system is connected to an uninterruptible power supply (UPS) (and the UPS is connected to a mains power source that is currently providing power), the transaction is committed without first flushing the processor cache to the non-volatile memory. If the computing system is not connected to a UPS (and is connected to a mains power source that is currently providing power), the transaction is not committed until the processor cache has been flushed to the non-volatile memory.

Committing transaction without first flushing processor cache to non-volatile memory when connected to UPS

A memory module stores a computing device type-specific parameter for each of a number of different types of computing devices. When the memory module is installed within a computing device, the computing device reads the computing device type-specific parameter for the particular type of computing device, and configures itself to use the memory module according to this parameter. As different types of memory modules become available, they are tested against different types of computing devices to determine the computing device type-specific parameter with which they should be programmed for each type of computing device.

Computing device-specific memory module

A memory module socket and a terminating resistor assembly. The terminating resistor assembly provides an elongate conductive bus bar and a plurality of conductive branches, wherein each conductive branch is in electronic communication with the elongate conductive bus bar through a resistor, wherein each conductive branch has a distal end disposed for contacting a signal pin within a memory module socket installed on a printed circuit board. A distal end of each conductive branch is inserted into a window on the connector shoulder adjacent to the slot of an empty memory module socket and engages a plurality of signal pins within the socket in response to the absence of a memory module in the slot. The plurality of signal pins engage contact pads on the memory module and are pushed out of contact with the conductive branch in response to the presence of a memory module in the slot.

Memory module socket with terminating apparatus

Computing devices have fan speeds governing airflows through the computing devices. The rack has a maximum airflow associated with a cooling component for the rack. The computing devices transmit their current airflows. A sum of the current airflows is determined. Where the sum is greater than the maximum airflow, the fan speeds of one or more selected computing devices are decreased. The fan speeds of lower priority computing devices may be reduced before the fan speeds higher priority computing devices are reduced. Fan speed reduction may be achieved in a centralized manner, by employing a centralized management component, or in a decentralized manner, without employing a centralized management component.

Fan speed control of rack devices where sum of device airflows is greater than maximum airflow of rack

One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. An alert is generated in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the predefined interval. The repeat-error threshold is set lower than the random-error threshold. A hashing process may be applied to the memory address of each detected error to map the location of the error in the memory system to a corresponding location in an electronic table.

Use of hashing function to distinguish random and repeat errors in a memory system

A power management server and method for managing power consumption is disclosed. According to one embodiment, a power management server data processing system is provided, where the power management server data processing system comprises a power management communication port to communicatively couple the power management server data processing system to a power-managed server data processing system and a system management processor coupled to the power management communication port. In the described embodiment, the system management processor comprises power management logic configured to receive power management data from the power-managed server data processing system, to generate a power management command utilizing the power management data, and to transmit the power management command to the power-managed server data processing system utilizing the power management communication port. Moreover, the power management data of the described embodiment comprises power management capability data.

Power management server for managing power consumption

A power-managed server and method for managing power consumption is disclosed. According to one embodiment, a power-managed server data processing system is provided among a plurality of server data processing systems which comprises a power management communication port to communicatively couple the power-managed server data processing system to a power management server data processing system of the plurality of server data processing systems. The power-managed server data processing system of the described embodiment further comprises a system management processor coupled to the power management communication port which comprises power-managed logic configured to transmit power management data to the power management server data processing system and to receive a power management command utilizing the power management communication port. Moreover, the power management command is generated utilizing the power management data, and the power management data comprises power management capability data.

Power-managed server and method for managing power consumption

A power-managed server data processing system comprises a bus configured to communicatively couple a power-managed server with a data processing system resource and a bus controller coupled to the bus. The bus controller comprises bus control logic configured to process a plurality of access requests associated with the bus, and power management logic configured to inhibit processing of a current access request of the plurality of access requests by the bus control logic for a power management delay time period. The power management delay time period is determined utilizing a processing latency time period associated with a prior access request of the plurality of access requests.

System and method for managing power usage of a data processing system subsystem

A hierarchical power management system comprises first and second power management controllers, a power management command combination element, a power management command terminator, a power-managed data processing system element, and a power management bus coupled between the power management controllers, power management command combination element, and power management command terminator.

Hierarchical system and method for managing power usage among server data processing systems

A distributed method and system for managing power usage among server data processing systems are disclosed. According to one embodiment, a server data processing system of a plurality of server data processing systems is provided, where the server data processing system comprises a power management communication port to communicatively couple the server data processing system to all other server data processing systems of the plurality of server data processing systems and a system management processor coupled to the power management communication port. In the described embodiment, the system management processor comprises communication logic configured to monitor power usage of all the other server data processing systems of the plurality, and power management logic configured to perform a power management operation on the server data processing system based upon the monitored power usage.

Growing community of inventors

Cary, NC, United States of America

Sumanta Kumar Bahali