Intel Corporation

Sumant Tapas

Eliezer Weissmann

Eugene Gorbatov

Russell Jerome Fenger

Rajshree Chabukswar

Hisham Abu Salah

Monica Gupta

Balaji Masanamuthu Chinnathurai

Guruprasad Settuvalli

Meghana Gudaram

Raj Kumar Subramaniam

Rajshree Arun Chabukswar

A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.

Technology for optimizing hybrid processor utilization

Growing community of inventors

Hillsboro, OR, United States of America

Sumant Tapas