Arm Limited

Sumant Kumar Thapliyal

Fakhruddin Ali Bohra

Vikash

Rajiv Kumar Roy

Manish Trivedi

Avinash Merugu

Abdullah Shahid

Deeksha Anandani

Veera Raghavulu Marella

Sumeet Sawant

Srinath Gopinath

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a bitcell and multiple straps including a first strap, a second strap, and a third strap. The first strap may couple the bitcell to ground. The second strap may couple the bitcell to a bitline. The third strap may couple the bitcell to a wordline within a boundary of the bitcell.

Bitcell wordline strapping circuitry

Various implementations described herein are directed to an integrated circuit having high density memory architecture. The integrated circuit may include a plurality of bank arrays having multiple segments of bitcells configured to share local control. The integrated circuit may include a plurality of control lines coupling the local control to each of the multiple segments of bitcells. In some instances, during activation of a segment of bitcells by the local control via one of the control lines, another segment of bitcells may be deactivated by the local control via another of the control lines.

High density memory architecture

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Bengaluru, India

Sumant Kumar Thapliyal