Texas Instruments Corporation

Sumant Dinkar Kale

Chunhua Hu

Venkateswar Reddy Kowkutla

Erkan Bilhan

Devanathan Varadarajan

Abhijeet Ashok Chachad

Ramakrishnan Venkatasubramanian

Lewis Nardini

Alan David Hales

An example includes a circuit including a first AND gate including a first input terminal, a second input terminal, and an output terminal, a second AND gate including a first input terminal, a second input terminal, and an output terminal, and a third AND gate including a first input terminal, a second input terminal, and an output terminal. The circuit also includes an OR gate including a first input terminal coupled to the output terminal of the first AND gate, a second input terminal coupled to the output terminal of the second AND gate, a third input terminal coupled to the output terminal of the third AND gate, and an output terminal.

Adaptive voltage scaling system for out of context functional safety SoC

A functional safety POR system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. Three stages of voltage monitoring are implemented to ensure redundancy.

On chip power on reset with integrated supervisory functions for a functional safety system

The optimal operating voltage of a complex SoC may be influenced by process variations. The operating voltages may be dynamically adjusted for optimal performance. These adjustments require a dynamic reconfiguration of the voltage monitoring thresholds in the power on reset circuitry of the SoC.

In described examples of circuitry and methods for testing multiple memories, a controller generates a sequence of commands to be applied to one or more of the memories, where each given command includes expected data, and a command address. Local adapters are individually coupled with the controller and with an associated memory. Each local adapter translates the command to a memory type of the associated memory, maps the command address to a local address of the associated memory, and provides test results to the controller according to read data from the local address of the associated memory and the expected data of the command.

Parallel memory self-testing

A large-scale integrated circuit with built-in self-repair (BISR) circuitry for enabling redundancy repair for embedded memories in each of a plurality of processor cores with embedded built-in self-test (BIST) circuitry. The BISR circuitry receives and decodes BIST data from the embedded memories into fail signature data in a physical-aware form on which repair analysis can be performed. The fail signature data is reformatted into a unified repair format, such that a fuse encoder circuit can be used to encode fuse patterns in that unified repair format for a repair entity for each of the embedded memories. The fuse patterns are reconfigured into the appropriate order for storing in shadow fuse registers associated with the specific embedded memories.

Centralized built-in soft-repair architecture for integrated circuits with embedded memories

A functional safety Power on Reset system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. A plurality of voltage monitoring stages is implemented to ensure redundancy.

On chip redundant system reset for out of context functional safety SoC

Apparatus and method for testing an integrated circuit. An integrated circuit includes circuitry to be tested, scan chain logic, and a test adapter. The scan chain logic is configured to transfer test data to and test results from the circuitry. The test adapter is configured to extract the test data from a packet received from an automated test control system and to transfer the test data to the scan chain logic. The test adapter is also configured to receive the test results from the scan chain logic, and to packetize the test result for transmission to the automated test control system.

Packet based integrated circuit testing

In an embodiment of the invention, a pipelined memory bank is tested by scanning test patterns into an integrated circuit. Test data is formed from the test patterns and shifted into a scan-in chain in the pipelined memory bank. The test data in the scan-in chain is launched into the inputs of the pipelined memory bank during a first clock cycle. Data from the outputs of the pipelined memory bank is captured in a scan-out chain during a second cycle where the time between the first and second clock cycles is equal to or greater than the read latency of the memory bank.

Growing community of inventors

Allen, TX, United States of America

Sumant Dinkar Kale