Freescale Semiconductor,inc.

Suman K Banerjee

Olin L Hartin

Radu Mircea Secareanu

Walter Parmon

Craig Jasper

Jay Paul John

Thuy B Dao

Enrique Ferrer

Sandra J Wipf

Alain C Duvallet

Philip Li

Alain C Duvalley

An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.

Noise isolation between circuit blocks in an integrated circuit chip

Apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect () configured to couple to a first region of the substrate, a first gate () coupled to the first interconnect and configured to receive a first differential input, a second interconnect () parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate () coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.

Electronic apparatus interconnect routing

Method and apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect () configured to couple to a first region of the substrate, a first gate () coupled to the first interconnect and configured to receive a first differential input, a second interconnect () parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate () coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.

Electronic apparatus interconnect routing and interconnect routing method for minimizing parasitic resistance

Flip-chip electronic devices () employ bumps () for coupling to an external substrate. Device cells () and bumps () are preferably arranged in clusters () where four bumps () substantially surround each device cell () or form a cross with the device cell () at the intersection of the cross. The bumps () are desirably spaced apart by the minimum allowable bump () pitch (L). Typically, each device cell () contains one or more active device regions () depending on the overall function. Complex devices () are formed by an X-Y array of the clusters (), where adjacent clusters () may share bumps () and/or device cells (). In a preferred embodiment, the bumps () form the outer perimeter () of the device (). The maximum device temperature and overall noise is reduced.

Electronic device with connection bumps

An integrated circuit includes a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region formed surrounding the p-well block region for providing noise isolation between the first circuit block and the second circuit block.

Methods are provided for forming a semiconductor device from a substrate comprising a bottom gate layer, a channel layer overlying the bottom gate layer, and a top gate structure formed over the channel layer. First, a hardmask comprising a first material interposed between a second material and a third material is deposited over a portion of the top gate structure. Then, the hardmask and top gate structure are encapsulated with an insulating material to form a spacer. A channel structure is formed from the channel layer, and the channel structure is disposed under the spacer. A bottom gate structure is formed from the bottom gate layer, and the bottom gate structure is disposed under the channel structure. Then, a source/drain contact is formed around the bottom gate structure.

Method of making planar double gate silicon-on-insulator structures

A system-on chip (SOC) () and method of isolating noise in a SOC, including a plurality of noise sensitive circuit blocks () and ESD protected pads (and). A VDD isolation pad () is connected to an N well ring () of the first noise sensitive circuit () to collect noise from the substrate () and isolate the circuit from the P well region (). A ground protected pad () is connected to an isolated P well () of a first noise sensitive circuit (). The ground pad () collects noise from the isolated P well () and sends it to ground. A dedicated ground isolation pad () is connected to a P well ring () of a second noise sensitive circuit (). The dedicated ground isolation pad () collects noise from the P well ring () and sends it to ground. The dedicated ground isolation pad () and the ground pad () collect noise that would normally propagate between the first and second noise sensitive circuits () and additional circuits that share the same substrate ().

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Chandler, AZ, United States of America

Suman K Banerjee