Intel Corporation

The Penn State Research Foundation

Other

University of California

University of Notre Dame Du Lac

Tahoe Research, Ltd.

Intel Corporationn

Suman Datta

Robert S Chau

Jack T Kavalieros

Justin K Brask

Mark L Doczy

Matthew V Metz

Brian S Doyle

Been-Yih Jin

Uday Shah

Amlan Majumdar

Marko Radosavljevic

Scott A Hareland

Gilbert W Dewey

Mantu K Hudait

Chris E Barns

Vijaykrishnan Narayanan

Douglas W Barlage

Anand S Murthy

Boyan Boyanov

Vivek K De

Dinesh Somasekhar

Markus Kuhn

Sangwoo Pae

Annalisa Cappellani

Shaofeng Yu

Xueqing Li

Ali Keshavarzi

James M Blackwell

Adrian B Sherrill

Sumeet Kumar Gupta

Ravi Pillarisetty

Rafael Rios

Nick Lindert

Peter G Tolchinsky

Joel Mark Fastenau

Christopher D Thomas

Dmitri Loubychev

Amy W K Liu

Bo Zheng

Tom Linton

Majumdar Amian

Mark T Bohr

Muhammad M Khellah

Shih-Lien L Lu

Yibin Ye

Fabrice Paillet

Stephen H Tang

Titash Rakshit

Aaron A Budrevich

Jose A Maiz

Nancy M Zelick

Ying Zhou

Ramune Nagisetty

Robert B Turkot, Jr

John Sampson

Sumitha George

Kaisheng Ma

Huichu Liu

Ramesh Vaddi

Ahmedullah Aziz

Nikhil Shukla

Willy Rachmady

Valery M Dubin

David L Kencke

Mark Y Liu

Andrew C Kummel

Martin D Giles

Timothy E Glassman

Jack Hwang

Lawrence D Wong

Anne E Miller

Mitchell C Taylor

Sunit Tyagi

Been Y Jin

Everett X Wang

Alexandre Schmid

Mark Stettler

Lucian Shifren

Ramakrishnan Krishnan

Marko Radosavlievic

Christopher G Parker

John Burghard

Jawar Singh

Saurabh Mookerjea

Amian Majumdar

Robert L Norman

David Simon, Legal Representative

Matthew V Mertz

Philippe Matagne

Ben Jin

Terence Bacuita

Moon Seok Kim

Kai Ni

Mahsa Shoaran

Unsuk Heo

Vinay Saripalli

Dheeraj Mohata

Saurabh Mookherjea

Tom Linton Jr

A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Method for fabricating transistor with thinned channel

An N-bit non-volatile multi-level memory cell (MLC) can include a lower electrode and an upper electrode spaced above the lower electrode. N ferroelectric material layers can be vertically spaced apart from one another between the lower electrode and the upper electrode, wherein N is at least 2 and at least one dielectric material layer having a thickness of less than 20 nm can be located between the N ferroelectric material layers.

Non-volatile multi-level cell memory using a ferroelectric superlattice and related systems

A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. Vacancies in the gate dielectric layer may be filled with capping layer material.

Gate electrode having a capping layer

A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.

Low power sense amplifier based on phase transition material

A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. The method includes depositing a dielectric layer on a substrate, followed by deposition of a capping layer in-situ over the dielectric layer prior to any high temperature processing.

Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I&#x2212;Vhysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two Istates at V=0.

Nonvolatile digital computing with ferroelectric FET

Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I-Vhysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two Istates at V=0.

A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

Extreme high mobility CMOS logic

A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.

Forming arsenide-based complementary logic on a single substrate

Disclosed are low power electronic devices configured to exploit the sub-threshold swing, unidirectional tunneling, and low-voltage operation of steep slope-tunnel tunnel field-effect transistors (TFET) to improve power-conversion efficiency and power-efficiency of electrical systems incorporating the TFET as an electrical component to perform energy harvesting, signal processing, and related operations. The devices include a HTFET-based rectifier having various topologies, a HTFET-based DC-DC charge pump converter, a HTFET-based amplifier having an amplifier circuit including a telescopic operational transconductance amplifier, and a HTFET-based SAR A/D converter having a HTFET-based transmission gate DFF. Any one of the devices may be used to generate a RF-powered system with improved power conversion efficiencies of power harvesters and power efficiencies of processing components within the system.

Low power nanoelectronics

Growing community of inventors

Beaverton, OR, United States of America

Suman Datta