Information Storage Devices, Inc.

Hyundai Electronics America, Inc.

Hynix Semiconductor America, Inc.

Terra Semiconductor, Inc.

Sukyoon Yoon

Hieu Van Tran

Trevor A Blyth

James Brennan, Jr

Pavel Klinger

Joo Young Yoon

A high-density flash EEPROM (Electrically Erasable Programmable Read Only Memory) unit cell and a memory array architecture including the same are disclosed. The flash EEPROM unit cell comprises a substrate on which field oxide layers are formed for isolating unit cells, a floating gate dielectric layer formed between the adjacent field oxide layers, wherein the floating gate dielectric layer includes a first dielectric layer and a second dielectric layer which are connected in parallel between a source and a drain formed on the substrate, and the thickness of the first dielectric layer is thicker than the second dielectric layer, a floating gate formed on the floating gate dielectric layer, a control gate dielectric layer formed on the floating gate; and a control gate formed on the control gate dielectric layer.

Flash EEPROM unit cell and memory array architecture including the same

A flash memory device includes a substrate having first and second wells. The first well is defined within the second well. A plurality of trenches defines the substrate into a plurality of sub-columnar active regions. The trenches is formed within the first well and extends into the second well. A plurality of flash memory cells are formed on each of the sub-columnar active regions.

High density flash memory architecture with columnar substrate coding

Instead of using a common substrate ( ) for each sector of a flash memory, trenches are used to isolate columnar active substrate regions ( ) of the substrate ( ), and independent access to each of these columnar regions ( ) is provided. First, the independent access to each of these columnar regions ( ) provides a capability for achieving more precise control over the voltage on the floating gates ( ). For example, flash memory in accordance with the present invention is better suited for multi-level storage (storing of more than 1 bit of information per cell). Second, the independent access to each of these columnar regions ( ) also provides a capability for areas of flash memory smaller than an entire sector to be erased at one time. Finally, since both programming and erasing is achieved by way of cold electron tunneling from the columnar active substrate region ( ), no high voltages need to be applied to either the drain ( ) or source ( ). This is advantageous in that the minimum distance required by cell punchthrough is reduced. Hence, higher densities of flash memory may be achieved.

Instead of using a common substrate (,) for each sector of a flash memory, trenches are used to isolate columnar active substrate regions (,) of the substrate (,), and independent access to each of these columnar regions (,) is provided. First, the independent access to each of these columnar regions (,) provides a capability for achieving more precise control over the voltage on the floating gates (,). For example, flash memory in accordance with the present invention is better suited for multi-level storage (storing of more than 1 bit of information per cell). Second, the independent access to each of these columnar regions (,) also provides a capability for areas of flash memory smaller than an entire sector to be erased at one time. Finally, since both programming and erasing is achieved by way of cold electron tunneling from the columnar active substrate region (,), no high voltages need to be applied to either the drain (,) or source (,). This is advantageous in that the minimum distance required by cell punchthrough is reduced. Hence, higher densities of flash memory may be achieved.

This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.

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Saratoga, CA, United States of America

Sukyoon Yoon